公开(公告)号：US11296031B2

公开(公告)日：2022-04-05

申请号：US16769548

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/762 ,  H01L29/06 ,  H01L21/765 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

公开(公告)号：US11222847B2

公开(公告)日：2022-01-11

申请号：US16469084

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US11031341B2

公开(公告)日：2021-06-08

申请号：US16474005

申请日：2017-03-29

Applicant: Intel Corporation ,  Md Altai Hossain ,  Kevin J Doran ,  Yu Amos Zhang ,  Zhiguo Qian

Inventor： Md Altai Hossain ,  Kevin J Doran ,  Yu Amos Zhang ,  Zhiguo Qian

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L23/13 ,  H01L25/065

Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

公开(公告)号：US10692847B2

公开(公告)日：2020-06-23

申请号：US15755533

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Daniel Sobieski ,  Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Merve Celikkol ,  Kyu Oh Lee ,  Kemal Aygun ,  Zhiguo Qian

IPC: H01L25/18 ,  H01L23/14 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.

公开(公告)号：US20200168553A1

公开(公告)日：2020-05-28

申请号：US16774508

申请日：2020-01-28

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

公开(公告)号：US20190341349A1

公开(公告)日：2019-11-07

申请号：US16474005

申请日：2017-03-29

Applicant: Kevin J. DORAN ,  MD Altaf HOSSAIN ,  Yu Amos ZHANG ,  Zhiguo QIAN ,  Intel Corporation

Inventor： MD Altaf Hossain ,  Kevin J Doran ,  Yu Amos Zhang ,  Zhiguo Qian

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

公开(公告)号：US10283453B2

公开(公告)日：2019-05-07

申请号：US15297005

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L21/768 ,  H01L23/538 ,  G06F17/50 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

公开(公告)号：US20180335465A1

公开(公告)日：2018-11-22

申请号：US15776979

申请日：2015-11-18

Applicant: Intel Corporation

Inventor： Mayue Xie ,  Simranjit S. Khalsa ,  Hemachandar Tanukonda Devarajulu ,  Deepak Goyal ,  Zhiguo Qian

IPC: G01R31/11 ,  G01R31/28

CPC classification number: G01R31/11 ,  G01R31/2853 ,  G01R31/2896 ,  G01R31/311

Abstract: An apparatus comprises a signal generator circuit, a test probe, a signal sensor circuit, and a defect detection circuit. The signal generator circuit is configured to generate an impulse test signal having an impulse waveform and adjust a bandwidth of the impulse test signal. The test probe is electrically coupled to the signal generator circuit and configured to apply the impulse test signal to a device under test (DUT). The signal sensor circuit is configured to sense a conducted test signal produced by applying the impulse test signal to the DUT with the test probe. The defect detection circuit is configured to generate an indication of a defect in the DUT using the conducted test signal.

公开(公告)号：US20180315688A1

公开(公告)日：2018-11-01

申请号：US16026824

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20180284185A1

公开(公告)日：2018-10-04

申请号：US15474674

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Mayue Xie ,  Zhiguo Qian ,  Jong-Ru Guo ,  Zhichao Zhang ,  Zuoguo Wu

IPC: G01R31/28

Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.