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公开(公告)号：US09804849B2
公开(公告)日：2017-10-31
申请号：US14887713
申请日：2015-10-20
Applicant: International Business Machines Corporation
Inventor： Ramon Bertran , Pradip Bose , Alper Buyuktosunoglu , Timothy J. Slegel
CPC classification number: G06F9/30145 , G06F1/28 , G06F8/41 , G06F9/30083 , G06F9/30181 , G06F11/3062 , G06F11/3433 , G06F11/36
Abstract: An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage.
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公开(公告)号：US09798546B2
公开(公告)日：2017-10-24
申请号：US14953722
申请日：2015-11-30
Applicant: International Business Machines Corporation
Inventor： Ramon Bertran , Pradip Bose , Alper Buyuktosunoglu , Timothy J. Slegel
CPC classification number: G06F9/30145 , G06F1/28 , G06F8/41 , G06F9/30083 , G06F9/30181 , G06F11/3062 , G06F11/3433 , G06F11/36
Abstract: An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage.
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公开(公告)号：US09588863B2
公开(公告)日：2017-03-07
申请号：US14519342
申请日：2014-10-21
Applicant: International Business Machines Corporation
Inventor： Ramon Bertran , Pradip Bose , Alper Buyuktosunoglu , Timothy J. Slegel
IPC: G06F17/50 , G06F11/00 , G06F13/00 , G06F9/45 , G01R31/28 , G06F11/30 , G06F11/34 , G06F9/455 , G06F13/10 , G06F13/12
CPC classification number: G06F9/30145 , G01R31/28 , G06F9/3005 , G06F9/44 , G06F9/455 , G06F11/00 , G06F11/3024 , G06F11/3414 , G06F11/3428 , G06F11/3457 , G06F13/10 , G06F13/12 , G06F15/7867 , G06F17/5009 , G06F17/5022
Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.
Abstract translation: 一个方面是一种方法，其包括由分析系统的处理器分析目标复合指令集计算机（CISC）处理器的指令集架构，以生成指令集架构的每个CISC体系结构指令变体的指令集简档 。 从对应于期望的应力标记类型的指令集简档确定针对CISC处理器的指令序列的组合。 期望的应力标记类型定义了表示目标CISC处理器感兴趣的功能的度量。 在执行每个指令序列时，针对期望的压力标记类型监视目标CISC处理器的性能。 基于相对于期望的应力标记类型执行指令序列的性能结果，将指令序列之一识别为与期望的压力标记类型最接近地对准。
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公开(公告)号：US20160378550A1
公开(公告)日：2016-12-29
申请号：US14950934
申请日：2015-11-24
Applicant: International Business Machines Corporation
Inventor： Ramon Bertran Monfort , Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Hans M. Jacobson , William J. Song , Karthik V. Swaminathan , Augusto J. Vega , Liang Wang
CPC classification number: G06F8/443 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/4843 , G06F9/4887 , G06F9/4893 , G06F9/543 , Y02D10/24
Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.
Abstract translation: 一个方面包括优化应用程序工作流程。 优化包括通过确定与嵌入式系统处理器的操作控制旋钮相关的至少一个基准度量来表征应用程序工作流程。 应用程序工作流执行由服务器系统支持的无线连接的系统集群的至少一个移动嵌入式系统遇到的实时计算任务。 应用程序工作流的优化还包括对满足至少一个运行时约束的应用工作流的至少一个基准度量执行优化操作。 输出作为执行优化操作的结果的注释工作流。
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公开(公告)号：US20160378367A1
公开(公告)日：2016-12-29
申请号：US14749680
申请日：2015-06-25
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Chen-Yong Cher , Ravi Nair
IPC: G06F3/06
CPC classification number: G06F9/30043 , G06F9/3863 , G06F11/00 , G06F11/30
Abstract: An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.
Abstract translation: 一方面包括接收包括存储器地址和写数据的写请求。 从存储器地址的存储器位置读取存储的数据。 基于确定存储器位置未被修改，将存储的数据与写入数据进行比较。 基于与写入数据匹配的存储数据，写入请求完成，而不将写入数据写入存储器，并且在静默存储位图中设置相应的静默存储位。 基于与写入数据不匹配的存储数据，将写入数据写入存储器位置，无声存储位被复位并且相应的修改位被置位。 为应用程序和操作系统中的至少一个提供对静默存储位图的访问。
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Patent Agency Ranking
公开(公告)号：US09507646B2
公开(公告)日：2016-11-29
申请号：US14619153
申请日：2015-02-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ramon Bertran , Pradip Bose , Alper Buyuktosunoglu , Timothy J. Siegel
CPC classification number: G06F9/52 , G06F1/04 , G06F9/48 , G06F9/4806 , G06F9/4825 , G06F9/485
Abstract: A time-of-day (TOD) clock is leveraged to provide a high-resolution measure of the real time that is suitable for the indication of date and time to perform cycle-level thread synchronization. A time-of-day value provided by the time-of-day clock is used in a spin lock, along with a configurable mask, to meet a specified condition. The condition is met at regular time intervals and at the same time for all the hardware threads to be synchronized. When the condition is met and synchronization is reached, execution of the threads continues ensuring that the activity generated on each thread is in synchronization.
Abstract translation: 使用时钟（TOD）时钟来提供适合于执行周期级线程同步的日期和时间的指示的实时的高分辨率度量。 日期时钟提供的时间值在自旋锁中与可配置的掩码一起使用，以满足指定的条件。 条件以规则的时间间隔满足，并且同时使所有硬件线程同步。 当满足条件并达到同步时，线程的执行将继续确保每个线程上生成的活动同步。
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公开(公告)号：US20160253264A1
公开(公告)日：2016-09-01
申请号：US14595737
申请日：2015-01-13
Applicant: International Business Machines Corporation
CPC classification number: G06F12/0862 , G06F9/46 , G06F9/5011 , G06F11/30 , G06F11/3024 , G06F11/3433 , G06F11/348 , G06F2201/88 , G06F2209/507 , G06F2209/508 , G06F2212/1024 , G06F2212/602 , G06F2212/6026 , G06F2212/6028
Abstract: In an approach for sharing memory bandwidth in one or more processors, a processor receives a first set of monitored usage information for one or more processors executing one or more threads. A processor calculates impact of hardware data prefetching for each thread of the one or more threads, based on the first set of monitored usage information. A processor adjusts prefetch settings for the one or more threads, based on the calculated impact of hardware data prefetching for each thread of the one or more threads.
Abstract translation: 在一种用于在一个或多个处理器中共享存储器带宽的方法中，处理器为执行一个或多个线程的一个或多个处理器接收第一组监视的使用信息。 处理器基于第一组监视的使用信息来计算对一个或多个线程的每个线程的硬件数据预取的影响。 处理器根据对一个或多个线程的每个线程的硬件数据预取的计算影响来调整一个或多个线程的预取设置。
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公开(公告)号：US20160239066A1
公开(公告)日：2016-08-18
申请号：US15137197
申请日：2016-04-25
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Augusto J. Vega
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
Abstract: Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.
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公开(公告)号：US20160232039A1
公开(公告)日：2016-08-11
申请号：US14619153
申请日：2015-02-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ramon Bertran , Pradip Bose , Alper Buyuktosunoglu , Timothy J. Slegel
IPC: G06F9/52
CPC classification number: G06F9/52 , G06F1/04 , G06F9/48 , G06F9/4806 , G06F9/4825 , G06F9/485
Abstract: A time-of-day (TOD) clock is leveraged to provide a high-resolution measure of the real time that is suitable for the indication of date and time to perform cycle-level thread synchronization. A time-of-day value provided by the time-of-day clock is used in a spin lock, along with a configurable mask, to meet a specified condition. The condition is met at regular time intervals and at the same time for all the hardware threads to be synchronized. When the condition is met and synchronization is reached, execution of the threads continues ensuring that the activity generated on each thread is in synchronization.
Abstract translation: 使用时钟（TOD）时钟来提供适合于执行周期级线程同步的日期和时间的指示的实时的高分辨率度量。 日期时钟提供的时间值在自旋锁中与可配置的掩码一起使用，以满足指定的条件。 条件以规则的时间间隔满足，并且同时使所有硬件线程同步。 当满足条件并达到同步时，线程的执行将继续确保每个线程上生成的活动同步。
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60.发明授权公开(公告)号：US09406368B2
公开(公告)日：2016-08-02
申请号：US14159798
申请日：2014-01-21
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Xiaochen Guo , Hillery C. Hunter , Jude A. Rivers , Vijayalakshmi Srinivasan
CPC classification number: G11C11/1675 , G11C7/04 , G11C11/1693
Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.
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