公开(公告)号：US20140151798A1

公开(公告)日：2014-06-05

申请号：US13692059

申请日：2012-12-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区和与沟道区相邻的栅电极。 栅电极被配置为控制在沟道区中形成的沟道的导电率，沟道区和漂移区沿着源极区和漏极区之间的第一方向设置，第一方向平行于第一主表面 。 沟道区域具有沿着第一方向延伸的第一脊的形状，并且晶体管包括邻近漂移区布置的第一场板。

公开(公告)号：US20140084362A1

公开(公告)日：2014-03-27

申请号：US13627215

申请日：2012-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Till Schloesser ,  Markus Zundel

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0883 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7828

Abstract: A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench.

Abstract translation: 半导体器件包括具有源极区，漏极区和栅电极的晶体管。 栅电极设置在布置在半导体衬底的顶表面中的第一沟槽中。 该装置还包括控制电极。 控制电极设置在布置在半导体衬底的顶表面中的第二沟槽中。 第二沟槽具有与第一沟槽的第一形状不同的第二形状。

公开(公告)号：US20130230956A1

公开(公告)日：2013-09-05

申请号：US13850037

申请日：2013-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Markus Zundel

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.

Abstract translation: 一种方法包括形成从半导体主体的第一表面延伸到半导体本体中的沟槽，使得第一沟槽部分和与第一沟槽部分相邻的至少一个第二沟槽部分，其中第一沟槽部分比第二沟槽部分宽 。 第一电极在至少一个第二沟槽部分中形成，并且通过第一介电层与半导体本体的半导体区域介电绝缘。 在至少一个第二沟槽部分中，在第一电极上形成电极间电介质层。 第二电极形成在电极间电介质层的至少一个第二沟槽部分中，并且在第一沟槽部分中，使得至少在第一沟槽部分中的第二电极与半导体本体电介质绝缘 第二电介质层。

公开(公告)号：US20220246744A1

公开(公告)日：2022-08-04

申请号：US17590685

申请日：2022-02-01

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Ingo Muri ,  Till Schloesser ,  Hans-Joachim Schulze ,  Olaf Storbeck

IPC: H01L29/49 ,  H01L25/07 ,  H01L29/78 ,  H01L29/40

Abstract: A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.

公开(公告)号：US11145745B2

公开(公告)日：2021-10-12

申请号：US16514292

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Christian Kampen ,  Andreas Meiser

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/06

Abstract: A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.

公开(公告)号：US10468405B2

公开(公告)日：2019-11-05

申请号：US15418491

申请日：2017-01-27

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Till Schloesser

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H03K17/687 ,  H01L27/06

Abstract: An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor substrate. The first transistor is of the same conductivity type as the second transistor. A first source region of the first transistor is electrically connected to a first source terminal via a first main surface of the semiconductor substrate. A second drain region of the second transistor is electrically connected to a second drain terminal via a first main surface of the semiconductor substrate. A first drain region of the first transistor and a second source region of the second transistor are electrically connected to an output terminal via a second main surface of the semiconductor substrate. The electric circuit further includes a control circuit operable to control a first gate electrode of the first transistor and a second gate electrode of the second transistor.

公开(公告)号：US20180026133A1

公开(公告)日：2018-01-25

申请号：US15653639

申请日：2017-07-19

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7833 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66575 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/7851

Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.

公开(公告)号：US09825148B2

公开(公告)日：2017-11-21

申请号：US15160525

申请日：2016-05-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/40 ,  H01L21/76 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

公开(公告)号：US20170221885A1

公开(公告)日：2017-08-03

申请号：US15418491

申请日：2017-01-27

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Till Schloesser

IPC: H01L27/088 ,  H01L29/08 ,  H03K17/687 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825 ,  H03K17/063 ,  H03K17/6871 ,  H03K2217/0081

Abstract: An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor substrate. The first transistor is of the same conductivity type as the second transistor. A first source region of the first transistor is electrically connected to a first source terminal via a first main surface of the semiconductor substrate. A second drain region of the second transistor is electrically connected to a second drain terminal via a first main surface of the semiconductor substrate. A first drain region of the first transistor and a second source region of the second transistor are electrically connected to an output terminal via a second main surface of the semiconductor substrate. The electric circuit further includes a control circuit operable to control a first gate electrode of the first transistor and a second gate electrode of the second transistor.

公开(公告)号：US20170162660A1

公开(公告)日：2017-06-08

申请号：US15437932

申请日：2017-02-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/417 ,  H01L27/15 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.