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    Local closed loop efficiency control using IP metrics
    53.
    发明授权
    Local closed loop efficiency control using IP metrics 有权

    公开(公告)号：US09696999B2

    公开(公告)日：2017-07-04

    申请号：US14109577

    申请日：2013-12-17

    申请人： Intel Corporation

    发明人： Inder M. Sodhi ,  Sanjeev S. Jahagirdar

    IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F1/08 ,  G06F9/38

    CPC分类号： G06F9/30196 ,  G06F1/08 ,  G06F9/3005 ,  G06F9/3869

    摘要： According to one embodiment, a processor includes an instruction decoder to decode instruction and a execution unit to execute instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit, a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit, and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics.

    Independent control of processor core retention states
    55.
    发明授权
    Independent control of processor core retention states 有权
    独立控制处理器核心保留状态

    公开(公告)号：US09081577B2

    公开(公告)日：2015-07-14

    申请号：US13729833

    申请日：2012-12-28

    申请人： Intel Corporation

    发明人： Shuan M. Conrad ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Anant S. Deval ,  Sanjeev S. Jahagirdar

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/172

    摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器， 当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。 响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值 电压值，独立于第二电压调节器。 存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。 描述和要求保护其他实施例。