公开(公告)号：US12080643B2

公开(公告)日：2024-09-03

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Juan G. Alzate Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5223 ,  H01L23/5226

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US11843054B2

公开(公告)日：2023-12-12

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Miriam Reshotko ,  Matthew Metz ,  Yih Wang ,  Gilbert Dewey ,  Jack Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Abhishek Sharma ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L23/5226 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78645 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11296229B2

公开(公告)日：2022-04-05

申请号：US16022494

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Yih Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Gilbert Dewey ,  Shriram Shivaraman ,  Matthew V. Metz

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.

公开(公告)号：US11245038B2

公开(公告)日：2022-02-08

申请号：US16490503

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Lee

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

公开(公告)号：US20220028861A1

公开(公告)日：2022-01-27

申请号：US17492487

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L27/108 ,  H01L25/065 ,  H01L23/64

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US11233040B2

公开(公告)日：2022-01-25

申请号：US16629915

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Yih Wang

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.

公开(公告)号：US10964701B2

公开(公告)日：2021-03-30

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Van H. Le ,  Gilbert William Dewey ,  Rafael Rios ,  Jack T. Kavalieros ,  Yih Wang ,  Shriram Shivaraman

IPC: H01L27/108 ,  G11C11/401 ,  G11C11/404 ,  G11C11/408 ,  G11C11/4096 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L27/13 ,  H01L49/02 ,  H01L29/22 ,  H01L29/24 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3105

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US10811595B2

公开(公告)日：2020-10-20

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee ,  Oleg Golonzka ,  Tahir Ghani ,  Ruth A. Brain ,  Yih Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

公开(公告)号：US20200043980A1

公开(公告)日：2020-02-06

申请号：US16594595

申请日：2019-10-07

Applicant: Intel Corporation

Inventor： Yih Wang ,  Patrick Morrow

IPC: H01L27/22 ,  H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

公开(公告)号：US20190393224A1

公开(公告)日：2019-12-26

申请号：US16488231

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Van Le

IPC: H01L27/108 ,  G11C11/408 ,  H01L29/786 ,  H01L23/528 ,  H01L29/24 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  H01L49/02 ,  H01L29/66

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.