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    Non-volatile memory devices including etching protection layers and methods of forming the same
    51.
    发明授权
    Non-volatile memory devices including etching protection layers and methods of forming the same 有权
    包括蚀刻保护层的非易失性存储器件及其形成方法

    公开(公告)号：US07589375B2

    公开(公告)日：2009-09-15

    申请号：US11642297

    申请日：2006-12-20

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

    摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

    Non-volatile memory devices including etching protection layers and methods of forming the same
    53.
    发明申请
    Non-volatile memory devices including etching protection layers and methods of forming the same 有权
    包括蚀刻保护层的非易失性存储器件及其形成方法

    公开(公告)号：US20070096197A1

    公开(公告)日：2007-05-03

    申请号：US11642297

    申请日：2006-12-20

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

    摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

    Node contact structures in semiconductor devices and methods of fabricating the same
    54.
    发明申请
    Node contact structures in semiconductor devices and methods of fabricating the same 有权
    半导体器件中的节点接触结构及其制造方法

    公开(公告)号：US20050151276A1

    公开(公告)日：2005-07-14

    申请号：US11032725

    申请日：2005-01-11

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L21/768 ,  H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

    摘要翻译： 静态随机存取存储器（SRAM）器件可以包括在其中具有源极/漏极区域的半导体衬底上的体MOS晶体管，体MOS晶体管上的绝缘层，以及在其中具有源极/漏极区域的薄膜晶体管 在体MOS晶体管上方的绝缘层上。 器件还可以包括在体MOS晶体管和薄膜晶体管之间的多层插头。 多层插头可以包括直接在体MOS晶体管的源极/漏极区域上并延伸穿过绝缘层的至少一部分的半导体插头，以及直接在薄膜的源极/漏极区域上的金属插塞 晶体管和半导体插头并延伸穿过绝缘层的至少一部分。 还讨论了相关方法。

    Methods of fabricating multi-layer nonvolatile memory devices
    57.
    发明授权
    Methods of fabricating multi-layer nonvolatile memory devices 有权
    制造多层非易失性存储器件的方法

    公开(公告)号：US07910433B2

    公开(公告)日：2011-03-22

    申请号：US12478538

    申请日：2009-06-04

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    SRAM devices having buried layer patterns
    58.
    发明授权
    SRAM devices having buried layer patterns 有权
    具有掩埋层图案的SRAM器件

    公开(公告)号：US07671389B2

    公开(公告)日：2010-03-02

    申请号：US11385473

    申请日：2006-03-21

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L31/112

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

    摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

    Semiconductor integrated circuits with stacked node contact structures
    59.
    发明授权
    Semiconductor integrated circuits with stacked node contact structures 有权
    具有堆叠节点接触结构的半导体集成电路

    公开(公告)号：US07479673B2

    公开(公告)日：2009-01-20

    申请号：US11033432

    申请日：2005-01-11

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/02

    CPC分类号： H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

    Semiconductor Integrated Circuits With Stacked Node Contact Structures
    60.
    发明申请
    Semiconductor Integrated Circuits With Stacked Node Contact Structures 审中-公开
    具有堆叠节点接触结构的半导体集成电路

    公开(公告)号：US20080023728A1

    公开(公告)日：2008-01-31

    申请号：US11868648

    申请日：2007-10-08

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/10

    CPC分类号： H01L27/1214 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。