公开(公告)号：US06934173B2

公开(公告)日：2005-08-23

申请号：US09893389

申请日：2001-06-28

申请人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Derner

发明人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Derner

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C29/04 ,  G11C29/14 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

摘要翻译： 一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。 感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。 在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。 提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。 写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。 提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。 多个电压源提供阵列和外围电路中所需的电压。 电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。 提供上电序列电路以控制芯片的上电。 提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。 芯片上还提供电路以支持各种类型的测试模式。

公开(公告)号：US06850452B2

公开(公告)日：2005-02-01

申请号：US10106558

申请日：2002-03-22

申请人： Brent Keeth ,  Layne G. Bunker

发明人： Brent Keeth ,  Layne G. Bunker

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L27/108 ,  G11C7/00

CPC分类号： H01L27/10805 ,  G11C5/025 ,  G11C5/063

摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

公开(公告)号：US06839265B2

公开(公告)日：2005-01-04

申请号：US10440575

申请日：2003-05-19

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/10885 ,  H01L23/5225 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： There is provided a bi-level bit line architecture. Specifically, a DRAM memory cell and cell array are provided that allow for six square feature area (6F2) cell sizes and avoid the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double-decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

摘要翻译： 提供了双级位线架构。 具体地，提供了允许六个正方形特征区域（6F 2）单元尺寸的DRAM存储单元和单元阵列，并且避免了信噪比问题。 独特的是，数字线条设计成像双层天桥路一样躺在彼此之上。 此外，该设计允许每个数字线路在两个导体层上布线，对于阵列的相同长度，以提供平衡阻抗。 现在噪声将作为两条线路上的共模噪声出现，而不是会降低感测操作的差模噪声。 此外，由于扭转设计，数字到数字耦合几乎消除了。

公开(公告)号：US06757200B2

公开(公告)日：2004-06-29

申请号：US10269599

申请日：2002-10-10

申请人： Brent Keeth ,  Charles Dennison

发明人： Brent Keeth ,  Charles Dennison

IPC分类号： G11C700

CPC分类号： G11C11/403 ,  G11C11/406 ,  Y10S257/907

摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.

摘要翻译： 本发明涉及具有用于存储数据的存储单元的集成电路装置和用于刷新存储单元中的数据的刷新电路。 在一个说明性实施例中，该设备包括具有存储元件，读/写访问设备和刷新访问设备的存储单元。 读/写数字线耦合到读/写访问设备，并且刷新数字线耦合到刷新访问设备。 读出放大器耦合到读/写数字线，并且输入/输出电路耦合到读/写数字线。 刷新读出放大器耦合到刷新数字线。 存储单元被构造成在相对较小，紧凑的区域中提供大的电荷存储容量。

公开(公告)号：US06710631B2

公开(公告)日：2004-03-23

申请号：US09909804

申请日：2001-07-20

申请人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Derner

发明人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Derner

IPC分类号： H03K300

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

公开(公告)号：US06697297B2

公开(公告)日：2004-02-24

申请号：US10230673

申请日：2002-08-29

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

摘要： A system and memory including a circuit for setting write latency and a write/valid indicator. Time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. A write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

摘要翻译： 包括用于设置写延迟的电路和写/有效指示符的系统和存储器。 时间裕度区域刚好在第一或前沿之后并且恰好在时钟信号的前导码的第二或后沿之后建立，使得等待时间设置将被发现是不可接受的，如果其引起写入使能信号在这些区域中的任一个中转变 。 写入/有效指示电路通过延迟时钟信号或写入使能信号并分别将它们的定时与未延迟写入使能信号或时钟信号的定时进行比较来创建起始和结束时间余量区域。

公开(公告)号：US06686786B2

公开(公告)日：2004-02-03

申请号：US09888498

申请日：2001-06-25

申请人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Derner

发明人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Derner

IPC分类号： H03K302

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

摘要翻译： 一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。 感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。 在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。 提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。 写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。 提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。 多个电压源提供阵列和外围电路中所需的电压。 电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。 提供上电序列电路以控制芯片的上电。 提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。 芯片上还提供电路以支持各种类型的测试模式。

公开(公告)号：US06683814B2

公开(公告)日：2004-01-27

申请号：US10278553

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06593192B2

公开(公告)日：2003-07-15

申请号：US09844184

申请日：2001-04-27

申请人： John K. Zahurak ,  Brent Keeth ,  Charles H. Dennison

发明人： John K. Zahurak ,  Brent Keeth ,  Charles H. Dennison

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648

摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.

摘要翻译： 根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。 这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。 绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

公开(公告)号：US06587804B1

公开(公告)日：2003-07-01

申请号：US09637088

申请日：2000-08-14

申请人： Brian Johnson ,  Brent Keeth

发明人： Brian Johnson ,  Brent Keeth

IPC分类号： G06F112

CPC分类号： G11C29/028 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254

摘要： A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

摘要翻译： 用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。 在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。 捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。 可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。