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51.发明授权Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor 失效用于在同时多线程（SMT）处理器中在单线程和多线程执行状态之间切换的方法和逻辑设备公开(公告)号：US07155600B2
公开(公告)日：2006-12-26
申请号：US10422648
申请日：2003-04-24
CPC分类号： G06F9/485
摘要： A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.
摘要翻译： 用于在同时多线程（SMT）处理器中的单线程和多线程执行状态之间切换的方法和逻辑设备提供了在单线程和多线程执行之间进行切换的机制。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑控制结束指令预取，调度新指令，中断处理和维护操作的事件序列，并等待处理器的操作完成以处理正在进行的指令。 然后，逻辑根据指定多个线程的使能状态的线程使能状态确定一个或多个线程，以重新分配各种资源，如果多个线程被指定用于进一步执行（多线程模式）或分配 如果进一步执行被指定为单线程模式，则基本上所有的资源到单个线程。 然后，处理器开始执行剩余的已启用线程。
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公开(公告)号：US07117126B2
公开(公告)日：2006-10-03
申请号：US09946217
申请日：2001-09-05
申请人： Michael Stephen Floyd , Ravi Kumar Arimilli , Daniel Mark Dreps , Frank David Ferraiolo , Kevin F. Reick
发明人： Michael Stephen Floyd , Ravi Kumar Arimilli , Daniel Mark Dreps , Frank David Ferraiolo , Kevin F. Reick
IPC分类号： G06F11/30
CPC分类号： H04L7/02 , H04L1/24 , H04L7/0004 , H04L7/0008 , H04L7/005
摘要： A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.
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53.发明授权Method and apparatus for interface failure survivability using error correction 有权使用纠错的接口故障生存性的方法和装置公开(公告)号：US07080288B2
公开(公告)日：2006-07-18
申请号：US10425423
申请日：2003-04-28
IPC分类号： G06F11/22
CPC分类号： H04L43/50 , G06F11/221 , H04L1/00 , H04L1/242
摘要： A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.
摘要翻译： 一种使用错误校正的接口故障生存性的装置的方法提供当接口的位数小于或等于可用纠错深度时的接口的操作。 初始化测试用于确定由于互连或电路故障导致的接口错误是否可以更正，还是禁用接口。 对于任何故障的位路径，在初始化或操作空闲期间的后续对齐可被禁用。 失败的位路径指示被确定并维护在硬件中，并用于绕过可能会破坏接口的后续校准。 可以产生指示全部故障的故障指示并用于响应于不可校正的状况而关闭接口和/或连接的子系统并请求立即修复。 可以产生指示可修正故障的第二故障指示并用于指示最终修复的需要。
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公开(公告)号：US07051221B2
公开(公告)日：2006-05-23
申请号：US10425399
申请日：2003-04-28
IPC分类号： G06F1/32
CPC分类号： G06F9/3017 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/30149 , G06F9/3802 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D50/20
摘要： A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.
摘要翻译： 微处理器包括具有动态功率节省电路的功能块，功能块控制电路和热控制单元。 功能块控制电路能够在检测到过温度条件时自动改变其相关功能块的性能特性。 热控制单元接收指示处理器温度超过阈值的过温度信号，并响应于该信号调用一个或多个功能块控制单元。 功能块控制单元通过减少处理器活动，降低处理器性能或两者来响应来自热控制单元的信号。 导致动态省电电路参与的活动减少。 功能块控制单元可以通过多种方式来抑制性能，包括减少处理器内可利用的并行性，暂停无序执行，减少有效的资源大小等。
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公开(公告)号：US06965839B2
公开(公告)日：2005-11-15
申请号：US10425395
申请日：2003-04-28
CPC分类号： G06F1/10
摘要： An integrated circuit device and system of devices in which a device interface incorporates dynamic, elastic calibration facilities. The interface includes a calibration manager and circuitry for monitoring the interface signals to detect the presence of signal skew, delay, or other degradation. If the monitor detects an out-of-calibration interface, the calibration manager initiates a dynamic calibration procedure. The calibration manager can also initiate the dynamic calibration procedure in response to an event such as the detection of a correctable error on the interface. By proactively monitoring the interface for degradation, the calibration manager is responsive to environmental changes as they occur and is efficient in its use of the calibration procedure by invoking it only when calibration is required.
摘要翻译： 集成电路器件和器件系统，其中器件接口包含动态弹性校准设备。 该接口包括校准管理器和用于监视接口信号以检测信号偏斜，延迟或其它劣化的存在的电路。 如果显示器检测到不合格界面，则校准管理器启动动态校准过程。 校准管理器还可以响应诸如在接口上检测到可校正错误的事件来启动动态校准过程。 通过主动监控界面的退化，校准管理器在环境变化发生时对其进行响应，并且只有在需要校准时才通过调用校准程序才有效。
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公开(公告)号：US06654917B1
公开(公告)日：2003-11-25
申请号：US09657106
申请日：2000-09-07
IPC分类号： G01R3128
CPC分类号： G01R31/318541 , G01R31/318544 , G01R31/318572
摘要： A method and apparatus for scanning the test and diagnostics control logic on a chip maintains the state of the chip in a frozen state as the scan of the normally free-running logic occurs. The chip is configured to select the test and diagnostics control logic if an instruction to scan the test and free-running logic is in the instruction register. A scan switch is configured to pass the scan output from the free-running logic to the test data output on the chip. Test data input is passed to the test and diagnostics control logic through the use of the scan select, as with the other logic units. The control interface is configured to feed a stop control and scan control signal back to the free-running logic under control of stop enable and scan enable signals. Outputs are forced to an electrically safe value by shadowing the driver control register, which controls the functional output.
摘要翻译： 用于扫描芯片上的测试和诊断控制逻辑的方法和装置在发生正常自由运行的逻辑的扫描时将芯片的状态保持在冻结状态。 如果扫描测试和自由运行逻辑的指令在指令寄存器中，则芯片被配置为选择测试和诊断控制逻辑。 扫描开关被配置为将扫描输出从自由运行的逻辑传递到芯片上的测试数据输出。 与其他逻辑单元一样，通过使用扫描选择将测试数据输入传递给测试和诊断控制逻辑。 控制接口配置为在停止使能和扫描使能信号的控制下将停止控制和扫描控制信号反馈给自由运行的逻辑。 输出通过遮蔽控制功能输出的驱动器控制寄存器被强制为电气安全值。
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57.发明授权Method and apparatus for providing cooperative fault recovery between a processor and a service processor 失效用于在处理器和服务处理器之间提供协作故障恢复的方法和装置公开(公告)号：US06643796B1
公开(公告)日：2003-11-04
申请号：US09574663
申请日：2000-05-18
IPC分类号： G06F1100
CPC分类号： G06F11/27 , G06F11/0724 , G06F11/0793
摘要： A method and apparatus for providing cooperative fault recovery between an operating system and a service processor allows fault detection and recovery capability utilizing a service processor while an operating system is running on a main processor. A register is provided within the main processor component for sending information to the service processor. An attention signal is provided to the service processor to indicate that the operating system has written information to the register and is requesting the service processor's attention. A JTAG standard interface is used to access the register from the service processor and an interrupt is provided to the operating system to indicate that the service processor has written information to the register and is requesting the operating system's attention.
摘要翻译： 用于在操作系统和服务处理器之间提供协作故障恢复的方法和装置允许在操作系统在主处理器上运行时利用服务处理器进行故障检测和恢复能力。 在主处理器组件内提供寄存器，用于向服务处理器发送信息。 向服务处理器提供注意信号以指示操作系统已经向寄存器写入信息并请求服务处理器的注意。 使用JTAG标准接口从服务处理器访问寄存器，并且向操作系统提供中断以指示服务处理器向寄存器写入信息并请求操作系统的注意。
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公开(公告)号：US09003417B2
公开(公告)日：2015-04-07
申请号：US13459398
申请日：2012-04-30
申请人： William Joseph Armstrong , Michael Stephen Floyd , Ronald Nick Kalla , Larry Scott Leitner , Balaram Sinharoy
发明人： William Joseph Armstrong , Michael Stephen Floyd , Ronald Nick Kalla , Larry Scott Leitner , Balaram Sinharoy
CPC分类号： G06F9/3851 , G06F9/50 , G06F11/3419 , G06F11/348 , G06F2201/88 , G06F2201/885
摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.
摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。
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公开(公告)号：US08271809B2
公开(公告)日：2012-09-18
申请号：US12424161
申请日：2009-04-15
CPC分类号： G06F11/348 , G06F11/3006 , G06F11/3024 , G06F11/3062 , G06F2201/88 , Y02D10/34
摘要： Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
摘要翻译： 说明性实施例估计多核微处理器芯片内的功率消耗。 授权用户选择要监视的一组活动。 一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。 该值包括计数乘以活动特有的权重因子。 该组活动被分组成子集。 将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。 每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。 将每个子集的缩放值相加，形成功率使用值。 功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。
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公开(公告)号：US08271765B2
公开(公告)日：2012-09-18
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译： 本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。 加载/存储单元在端口接收第一条指令。 响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。 然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。 当第一位被激活时，指令排序单元阻止重新发行的第一条指令。 处理器单元确定第一指令的拒绝类。 指令排序单元启动定时器。 定时器的长度取决于第一条指令的拒绝类型。 指令排序单元重置响应定时器超时的第一位。 响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。
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