公开(公告)号：US07648871B2

公开(公告)日：2010-01-19

申请号：US11163523

申请日：2005-10-21

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Kaushik A. Kumar ,  Carl Radens

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Kaushik A. Kumar ,  Carl Radens

IPC分类号： H01L21/8238

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，反相源极/漏极金属触点的下部具有约0.03mum2至约3.15mum2的横截面积，并且这种反向的源极/漏极金属触点与FET的栅电极间隔开一个 距离范围从约0.001毫米到约5毫米。

公开(公告)号：US20090233444A1

公开(公告)日：2009-09-17

申请号：US12046151

申请日：2008-03-11

申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

IPC分类号： H01L21/306 ,  C09K13/00

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

公开(公告)号：US07528065B2

公开(公告)日：2009-05-05

申请号：US11333068

申请日：2006-01-17

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

公开(公告)号：US20090072410A1

公开(公告)日：2009-03-19

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

公开(公告)号：US20090039331A1

公开(公告)日：2009-02-12

申请号：US11834851

申请日：2007-08-07

申请人： Lawrence A. Clevenger ,  Bruce G. Elmegreen ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Lia Krusin-Elbaum ,  Chung H. Lam ,  Dennis M. Newns

发明人： Lawrence A. Clevenger ,  Bruce G. Elmegreen ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Lia Krusin-Elbaum ,  Chung H. Lam ,  Dennis M. Newns

IPC分类号： H01L47/00 ,  G11C11/00

CPC分类号： G11C17/165 ,  G11C13/0004 ,  G11C13/0069 ,  G11C17/16 ,  G11C2013/0078 ,  G11C2013/008 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： Structures including a phase change material are disclosed. The structure may include a first electrode; a second electrode; a phase change material electrically connecting the first electrode and the second electrode for passing a current therethrough; and a tantalum nitride heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).

摘要翻译： 公开了包括相变材料的结构。 该结构可以包括第一电极; 第二电极; 电连接第一电极和第二电极以使电流通过的相变材料; 以及围绕所述相变材料的氮化钽加热器层，用于通过向所述相变材料施加第二电流来将所述相变材料转换成非晶态绝缘状态和结晶导电状态。 该结构可以用作保险丝或相变材料随机存取存储器（PRAM）。

公开(公告)号：US07439172B2

公开(公告)日：2008-10-21

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US20080254643A1

公开(公告)日：2008-10-16

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20080243972A1

公开(公告)日：2008-10-02

申请号：US11694183

申请日：2007-03-30

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L.C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L.C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： G06F15/02

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

公开(公告)号：US07402532B2

公开(公告)日：2008-07-22

申请号：US11499220

申请日：2006-08-04

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20080171432A1

公开(公告)日：2008-07-17

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一电介质层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。