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84 条记录 (耗时 0.035 秒)

    Digital random noise generator
    51.
    发明授权
    Digital random noise generator 失效
    数字随机噪声发生器

    公开(公告)号：US06910165B2

    公开(公告)日：2005-06-21

    申请号：US09795899

    申请日：2001-02-28

    申请人： Howard H. Chen ,  Li-Kong Wang ,  Louis L. Hsu ,  Sang H. Dhong ,  Tin-chee Lo

    发明人： Howard H. Chen ,  Li-Kong Wang ,  Louis L. Hsu ,  Sang H. Dhong ,  Tin-chee Lo

    IPC分类号： G01R31/28 ,  H03K3/84 ,  G06F11/00

    CPC分类号： H03K3/84 ,  G01R31/2841

    摘要： A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device. A second random pattern generator circuit may be provided for generating second sets of random bit pattern signals for receipt by each of the associated oscillator circuit devices in order to frequency adjust in a random manner, each of the oscillator signals.

    摘要翻译： 用于产生用于测试电子设备的随机噪声的系统和方法包括：第一随机模式发生器电路，用于产生第一组随机位模式信号; 每个接收触发输入信号的一个或多个延迟装置和随机位模式信号组，用于响应于相应的延迟输出信号而产生，每个延迟输出信号相对于相应的触发信号在时间上延迟，延迟时间由 接收到位模式集; 以及与相应的一个或多个延迟装置相关联的振荡器电路装置，用于从其接收相应的延迟输出信号并产生相应的振荡信号，所产生的每个振荡器信号用于产生人造随机噪声，以仿真电子中的实际噪声环境 设备。 可以提供第二随机模式发生器电路，用于产生第二组随机位模式信号，以便由每个相关联的振荡器电路装置接收，以便随机地调整每个振荡器信号。

    Distributed DC voltage generator for system on chip
    52.
    发明授权
    Distributed DC voltage generator for system on chip 失效
    分布式直流电压发生器，用于片上系统

    公开(公告)号：US06803805B2

    公开(公告)日：2004-10-12

    申请号：US10118753

    申请日：2002-04-09

    申请人： Li-Kong Wang ,  Louis L. Hsu ,  Fanchieh Yee

    发明人： Li-Kong Wang ,  Louis L. Hsu ,  Fanchieh Yee

    IPC分类号： G05F302

    CPC分类号： G06F1/26 ,  Y10T307/25

    摘要： A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

    摘要翻译： 提供了一种芯片系统（SOC电压发生器）系统，用于向具有SOC设计的芯片上的多个单元提供至少一个电压电平。 该系统包括分布在整个芯片上的多个本地直流电压发生器，每个局部直流电压发生器独立地向多个单元中的至少一个单元提供电压，每个局部直流电压发生器包括输出一个泵控制信号的调节器系统; 以及泵系统，接收所述一个泵控制信号，并根据所述一个泵控制信号输出至少一个电压电平。 此外，提供了一种用于向具有SOC设计的芯片上的多个单元提供电压的方法。 该方法包括在整个芯片上分配多个局部DC电压发生器的步骤; 并且经由所述多个本地DC电压发生器向所述多个单元提供至少一个电压电平。

    Hierarchical built-in self-test for system-on-chip design
    53.
    发明授权
    Hierarchical built-in self-test for system-on-chip design 有权
    分层内置自检系统级芯片设计

    公开(公告)号：US06728916B2

    公开(公告)日：2004-04-27

    申请号：US09863952

    申请日：2001-05-23

    申请人： Howard H. Chen ,  Louis L. Hsu ,  Li-Kong Wang

    发明人： Howard H. Chen ,  Louis L. Hsu ,  Li-Kong Wang

    IPC分类号： G01R3128

    CPC分类号： G06F11/27

    摘要： Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

    摘要翻译： 分层内置的自检方法和安排，用于验证系统功能。 因此，提供了一种有效的内置自检方法，用于进行完整的片上系统测试，以确保片上系统设计的电路可靠性和性能。 作为一个额外的优势，系统级芯片应用程序的开发成本有所降低。

    Three-dimensional island pixel photo-sensor
    54.
    发明授权
    Three-dimensional island pixel photo-sensor 有权
    三维岛像素光电传感器

    公开(公告)号：US06720595B2

    公开(公告)日：2004-04-13

    申请号：US09922077

    申请日：2001-08-06

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    IPC分类号： H01L31062

    CPC分类号： H01L27/14634 ,  H01L27/1463 ,  H01L27/14643

    摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

    摘要翻译： 公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。 利用本发明，侧壁垂直于接收入射光的光电二极管的表面。 感光侧壁包括当用光照射时引起电子转移的结区域。 侧壁包围围绕每个岛芯的四个垂直侧壁。 逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

    Multi-port memory device and system for addressing the multi-port memory device
    55.
    发明授权
    Multi-port memory device and system for addressing the multi-port memory device 失效

    公开(公告)号：US06594196B2

    公开(公告)日：2003-07-15

    申请号：US09725967

    申请日：2000-11-29

    申请人： Louis L Hsu ,  Tin-chee Lo ,  Li-Kong Wang

    发明人： Louis L Hsu ,  Tin-chee Lo ,  Li-Kong Wang

    IPC分类号： G11C800

    CPC分类号： G06F13/18 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/405

    摘要： A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated. A system for addressing the multi-port memory array includes a conflict detector for detecting a conflict between two or more of the row address signals to generate a conflict control signal corresponding to the conflict detected, a priority logic circuit for performing a logic operation with respect to the request command signals based on a predetermined priority logic to generate prioritized signals, and a selection unit for selecting one of a request command signal and a prioritized signal corresponding to the request command signal in response to the conflict control signal, where a signal selected by the selection unit selects a corresponding one of the row address signals.

    Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same
    56.
    发明授权
    Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same 有权
    具有SRAM，DRAM和闪速存储器的集成芯片及其制造方法

    公开(公告)号：US06556477B2

    公开(公告)日：2003-04-29

    申请号：US09861788

    申请日：2001-05-21

    申请人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

    IPC分类号： G11C1134

    CPC分类号： H01L27/105 ,  G11C11/005 ,  H01L27/1052

    摘要： A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.

    摘要翻译： 提出了在一个衬底上制造的半导体存储器系统，其包括SRAM器件，DRAM器件和闪存器件。 在一个实施例中，SRAM器件是高电阻负载SRAM器件。 在另一个实施例中，DRAM器件是深沟槽DRAM器件。 还提出了一种用于在具有SRAM器件，DRAM器件和闪存器件的一个衬底上制造存储器系统的方法。

    Integrated redundancy architecture system for an embedded DRAM
    57.
    发明授权
    Integrated redundancy architecture system for an embedded DRAM 有权
    嵌入式DRAM的集成冗余架构系统

    公开(公告)号：US06542973B2

    公开(公告)日：2003-04-01

    申请号：US09898434

    申请日：2001-07-03

    申请人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata ,  Gregory J. Fredeman

    发明人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata ,  Gregory J. Fredeman

    IPC分类号： G06F1200

    CPC分类号： G11C29/846 ,  G06F12/0893

    摘要： An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from a SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed. The integrated redundancy eDRAM architecture system enables data to be sent and received to and from the eDRAM macro system without adding any extra delay to the data flow, thereby protecting data flow pattern integrity.

    摘要翻译： 公开了一种用于具有宽数据带宽和宽内部总线宽度的嵌入式DRAM宏系统的集成冗余eDRAM架构系统，其为eDRAM宏系统的有缺陷的列和行提供列和行冗余。 在eDRAM宏测试模式期间，每个微小区块的有缺陷的列和行的内部生成的列和行地址存储在诸如保险丝库的存储器件中，以便在eDRAM的每个周期期间快速检索信息 操作提供类似SRAM的操作。 列转向电路引导列冗余元件来替换有缺陷的列元素。 根据是否正在执行读取或写入操作，冗余信息是从SRAM熔丝数据存储设备提供的，或者从TAG存储设备提供的。 集成冗余eDRAM架构系统使数据能够从eDRAM宏系统发送和接收数据，而不会对数据流增加任何额外的延迟，从而保护数据流模式的完整性。

    Self-refresh on-chip voltage generator
    58.
    发明授权
    Self-refresh on-chip voltage generator 失效
    自刷新片上电压发生器

    公开(公告)号：US06411157B1

    公开(公告)日：2002-06-25

    申请号：US09606650

    申请日：2000-06-29

    申请人： Louis L. Hsu ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Li-Kong Wang

    IPC分类号： G05F302

    CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/073

    摘要： A voltage control system and methodology for maintaining internally generated voltage levels in a semiconductor chip. The method comprises the steps of intermittently sampling an internal voltage supply level during a low power or “sleep” mode of operation; comparing the internal voltage supply level against a predetermined voltage reference level; and, activating a voltage supply generator for increasing the internal voltage supply level when the internal voltage supply level falls below the predetermined voltage reference level. The voltage supply generator is subsequently deactivated when the voltage supply level is restored to the predetermined voltage reference level. The sampling cycle may be appropriately tailored according to chip condition, chip temperature, and chip size. In one embodiment, the voltage control system and methodology is implemented in DRAM circuits during a refresh operation. The voltage levels that are suitable for sampling including DRAM band-gap reference voltage, boost wordline line voltage, wordline low voltage, bitline high voltage and bitline equalization voltages.

    摘要翻译： 一种用于维持半导体芯片内部产生的电压电平的电压控制系统和方法。 该方法包括以下步骤：在低功率或“睡眠”操作模式期间间歇地采样内部电压供应电平; 将内部电压供应电平与预定电压参考电平进行比较; 以及当所述内部电压供应电平低于所述预定电压参考电平时激活用于增加所述内部电压供应电平的电压源发生器。 当电压供应电平恢复到预定电压参考电平时，电压发生器随后被去激活。 采样周期可以根据芯片条件，芯片温度和芯片尺寸进行适当调整。 在一个实施例中，电压控制系统和方法在刷新操作期间在DRAM电路中实现。 适用于采样的电压电平，包括DRAM带隙参考电压，升压字线电压，字线低电压，位线高电压和位线均衡电压。