公开(公告)号：US20200312732A1

公开(公告)日：2020-10-01

申请号：US16903458

申请日：2020-06-17

Applicant: MEDIATEK INC.

Inventor： Yen-Yao CHI ,  Nai-Wei LIU ,  Ta-Jen YU ,  Tzu-Hung LIN ,  Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US20190131233A1

公开(公告)日：2019-05-02

申请号：US16232129

申请日：2018-12-26

Applicant: MEDIATEK INC.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

公开(公告)号：US20190043848A1

公开(公告)日：2019-02-07

申请号：US16043326

申请日：2018-07-24

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  I-Hsuan PENG ,  Tzu-Hung LIN

IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

公开(公告)号：US20180269164A1

公开(公告)日：2018-09-20

申请号：US15906098

申请日：2018-02-27

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/043 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.

公开(公告)号：US20170287877A1

公开(公告)日：2017-10-05

申请号：US15624790

申请日：2017-06-16

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.

公开(公告)号：US20170278832A1

公开(公告)日：2017-09-28

申请号：US15618210

申请日：2017-06-09

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.

公开(公告)号：US20170250165A1

公开(公告)日：2017-08-31

申请号：US15592488

申请日：2017-05-11

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Wei-Che HUANG ,  Tzu-Hung LIN

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure. the third semiconductor package is coupled to the second RDL structure by second vias passing through a second molding compound between the third semiconductor package and the second RDL structure.

公开(公告)号：US20170141041A1

公开(公告)日：2017-05-18

申请号：US15338652

申请日：2016-10-31

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Nai-Wei LIU ,  I-Hsuan PENG ,  Wei-Che HUANG

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.

公开(公告)号：US20170084525A1

公开(公告)日：2017-03-23

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L23/498 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US20170040266A1

公开(公告)日：2017-02-09

申请号：US15331016

申请日：2016-10-21

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU ,  Wei-Che HUANG ,  Che-Ya CHOU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装，其包括具有第一表面和与第一基板相对的第二表面的第一再分布层（RDL）结构。 第一RDL结构包括靠近第一RDL结构的第一表面的多个第一导电迹线。 天线图案靠近第一RDL结构的第二表面设置。 第一半导体管芯设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构通过第一RDL结构的多个第一导电迹线与天线图案间隔开。