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    REFRESH-RELATED ACTIVATION IMPROVEMENTS
    51.
    发明申请
    REFRESH-RELATED ACTIVATION IMPROVEMENTS 有权

    公开(公告)号：US20210225433A1

    公开(公告)日：2021-07-22

    申请号：US17159706

    申请日：2021-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

    IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

    Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

    Memory with partial bank refresh
    52.
    发明授权
    Memory with partial bank refresh 有权

    公开(公告)号：US11062755B2

    公开(公告)日：2021-07-13

    申请号：US16693949

    申请日：2019-11-25

    Applicant: Micron Technology, Inc.

    Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC: G11C7/00 ,  G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

    Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

    Memory with automatic background precondition upon powerup
    53.
    发明授权
    Memory with automatic background precondition upon powerup 有权

    公开(公告)号：US10990317B2

    公开(公告)日：2021-04-27

    申请号：US16553859

    申请日：2019-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

    IPC: G06F3/06 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4072 ,  G11C11/4091

    Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.

    SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS
    54.
    发明申请
    SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20210064461A1

    公开(公告)日：2021-03-04

    申请号：US16554958

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: G06F11/10

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

    MEMORY WITH PARTIAL ARRAY REFRESH
    55.
    发明申请
    MEMORY WITH PARTIAL ARRAY REFRESH 审中-公开

    公开(公告)号：US20200211636A1

    公开(公告)日：2020-07-02

    申请号：US16237013

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/10

    Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

    METHODS AND SYSTEMS FOR IMPROVING POWER DELIVERY AND SIGNALING IN STACKED SEMICONDUCTOR DEVICES
    56.
    发明申请
    METHODS AND SYSTEMS FOR IMPROVING POWER DELIVERY AND SIGNALING IN STACKED SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190067252A1

    公开(公告)日：2019-02-28

    申请号：US16115492

    申请日：2018-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/64

    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

    Apparatuses and methods for unit identification in a master/slave memory stack
    59.
    发明授权
    Apparatuses and methods for unit identification in a master/slave memory stack 有权
    主/从存储器堆栈中单元识别的设备和方法

    公开(公告)号：US08817547B2

    公开(公告)日：2014-08-26

    申请号：US13709792

    申请日：2012-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

    IPC: G11C7/10

    CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

    Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

    Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

    Voltage regulation distribution for stacked memory
    60.
    发明授权
    Voltage regulation distribution for stacked memory 有权

    公开(公告)号：US11816357B2

    公开(公告)日：2023-11-14

    申请号：US17400914

    申请日：2021-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Brian P. Callaway

    IPC: G06F3/00 ,  G06F3/06 ,  G11C5/14

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C5/147

    Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

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