公开(公告)号：US20170047289A1

公开(公告)日：2017-02-16

申请号：US14821874

申请日：2015-08-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a ground layer disposed on the substrate, a stacking structure having a plurality of conductive layers and a plurality of insulating layers alternatively stacked on the ground layer and a plurality of memory strings penetrating through the stacking structure. The ground layer includes a metal layer. The memory strings electrically contact with the metal layer.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，设置在衬底上的接地层，具有多个导电层和交替层叠在接地层上的多个绝缘层的堆叠结构以及贯穿堆叠结构的多个存储器串。 接地层包括金属层。 存储器串与金属层电接触。

公开(公告)号：US20160204102A1

公开(公告)日：2016-07-14

申请号：US14596257

申请日：2015-01-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/06 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0688 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11551 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising a substrate having a staircase region comprising N steps, wherein N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising a plurality of sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps to form respective contact regions; and a plurality of connectors formed in the respective contact regions, and the connectors extending downwardly to connect a bottom layer under the multi-layers.

Abstract translation: 提供三维（3D）半导体器件，其包括具有包括N个步骤的阶梯区域的衬底，其中N是整数1或更大; 在衬底上具有多层的叠层，并且所述多层包括与衬底上的绝缘层交替的有源层，所述堆叠包括形成在衬底上的多个子堆叠以及相对于N布置的子堆叠 形成各个接触区域的步骤; 以及形成在各个接触区域中的多个连接器，并且连接器向下延伸以连接多层下的底层。

公开(公告)号：US09373403B1

公开(公告)日：2016-06-21

申请号：US14790461

申请日：2015-07-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G11C16/04 ,  G11C16/06 ,  G11C5/06 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  H01L27/11582

Abstract: The present invention relates to 3D memory devices and methods for programming such devices, and more particularly to memory devices having control circuitry which is responsive to the indicator memory to apply a first control voltage to a selected one of the horizontal structures, apply a second control voltage to a non-selected one of the horizontal structures, and apply a third control voltage to an excluded one of the horizontal structures.

Abstract translation: 本发明涉及用于对这种设备进行编程的3D存储器件和方法，更具体地说，涉及具有控制电路的存储器件，该控制电路响应于指示存储器将第一控制电压施加到所选择的一个水平结构，施加第二控制 电压到未被选择的一个水平结构，并且将第三控制电压施加到排除的一个水平结构。

公开(公告)号：US09343322B2

公开(公告)日：2016-05-17

申请号：US14158589

申请日：2014-01-17

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: G11C5/06 ,  H01L21/308 ,  G11C7/00 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/306 ,  H01L27/115

CPC classification number: H01L21/308 ,  G11C7/00 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a plurality of stacks of alternating active strips and insulating strips. The insulating strips have effective oxide thicknesses (EOT) so that the stacks have non-simple spatial periods on a line through the alternating active strips and insulating strips. A plurality of conductive lines are arranged orthogonally over, and have surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the active strips in the stacks and the conductive lines. Memory elements are disposed in the interface regions, which establish a 3D array of memory cells accessible via the plurality of active strips and the plurality of conductive lines. The insulating strips in the stacks can include a first group of strips having a first EOT and a second group of strips having a second EOT that is greater than the first EOT.

Abstract translation: 存储器件包括交替的有源条和绝缘条的多个叠层。 绝缘条具有有效的氧化物厚度（EOT），使得堆叠在通过交替的有源条和绝缘条的线上具有非简单的空间周期。 在多个叠层中正交布置多个导线，并且具有与多个叠层一致的表面，在叠层和导电线中的活动带的侧表面之间的交叉点限定出界面区域的多层阵列。 存储器元件设置在接口区域中，其建立经由多个有源条带和多个导电线路可访问的存储器单元的3D阵列。 堆叠中的绝缘条可以包括具有第一EOT的第一组条带和具有大于第一EOT的第二EOT的第二组条带。

公开(公告)号：US20160005748A1

公开(公告)日：2016-01-07

申请号：US14857651

申请日：2015-09-17

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/11582

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL).

Abstract translation: 大致描述，存储器件具有横向划分成字线的多层导电层。 垂直取向的柱子各自包括在柱和层之间的交叉点处的串联存储器单元。 字符串选择线在导电层之上运行，并定义柱的选择栅。 位线在SSL之上运行。 支柱布置在具有单元单元面积α的规则网格上，并且相邻的串选择线具有至少与（α/ pBL）一样大的位线方向上的相应宽度。 接地选择线在导电层下方延伸并定义支柱的接地选择门。 接地选择线也可以具有至少与（α/ pBL）一样大的位线方向上的相应宽度。

公开(公告)号：US20160005713A1

公开(公告)日：2016-01-07

申请号：US14324373

申请日：2014-07-07

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/37001

Abstract: A three dimensional stacked multi-chip structure including M chips, a first conductive pillar, and N second conductive pillars is provided. Each chip has a common connection area and a chip-enable area, and includes a substrate and a patterned circuit layer disposed on the substrate. The patterned circuit layer includes an active element, at least one common conductive structure in the common connection area, and N chip-enable conductive structures in the chip-enable area. The first conductive pillar connects the common conductive structure of the M chips. Each second conductive pillar connects one of the N chip-enable conductive structures of the M chips. The chip-conductive areas of the M chips have different conducting states. N is large than 1, M is large than 2, and M is smaller than or equal to 2N.

Abstract translation: 提供了包括M个芯片，第一导电柱和N个第二导电柱的三维堆叠多芯片结构。 每个芯片具有公共连接区域和芯片使能区域，并且包括衬底和设置在衬底上的图案化电路层。 图案化电路层包括有源元件，公共连接区域中的至少一个公共导电结构和芯片使能区域中的N个芯片使能导电结构。 第一导电柱连接M芯片的公共导电结构。 每个第二导电柱连接M个芯片的N个芯片使能导电结构之一。 M芯片的芯片导电区域具有不同的导通状态。 N大于1，M大于2，M小于或等于2N。

公开(公告)号：US09041068B2

公开(公告)日：2015-05-26

申请号：US14042776

申请日：2013-10-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/118

CPC classification number: H01L27/11803 ,  H01L27/10897 ,  H01L27/11529 ,  H01L27/11807 ,  H03K19/17704

Abstract: A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.

Abstract translation: 提供了3D半导体器件及其3D逻辑阵列结构。 3D半导体器件包括阵列结构，外围线结构和3D逻辑阵列结构。 阵列结构具有位于阵列结构侧的Y触点。 Y在MN-1到MN之间。 Y，M和N是自然数。 M大于或等于2. 3D逻辑阵列结构包括N组栅电极，输入电极和Y输出电极。 每组栅电极具有M个栅电极。 Y输出电极连接Y触点。 M·N栅电极和输入电极连接外围线结构。

公开(公告)号：US20150130066A1

公开(公告)日：2015-05-14

申请号：US14076376

申请日：2013-11-11

Applicant: MACRONIX INTERNATIONAL CO., LTD

Inventor： Shih-Hung Chen

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers.

Abstract translation: 提供一种集成电路装置及其制造方法。 集成电路器件包括多个导电层，多个电介质层和多个第一阻挡层。 导电层沿第一方向延伸。 电介质层平行于导电层，并且导电层和电介质层以替代布置设置。 第一阻挡层设置在导电层和电介质层之上。 第一停止层不与导电层接触。

公开(公告)号：US20150084203A1

公开(公告)日：2015-03-26

申请号：US14038526

申请日：2013-09-26

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76838 ,  G11C16/0483 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.

Abstract translation: 形成接触结构的方法包括形成交替的有源层和绝缘层的叠层。 堆叠包括第一和第二子堆叠，每个子层具有由绝缘层分隔的活性层。 每个子堆叠的有源层包括上边界活性层。 在给定的蚀刻工艺中，在第一和第二子堆叠之间形成具有与绝缘层的蚀刻时间不同的蚀刻时间的子堆叠绝缘层。 访问上边界有源层，之后访问剩余的有源层以在有源层上创建着陆区域的初步结构。 层间导体形成为延伸到着陆区域，层间导体通过绝缘材料彼此分开。

公开(公告)号：US20150060958A1

公开(公告)日：2015-03-05

申请号：US14016308

申请日：2013-09-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Erh-Kun Lai

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28282 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers are interlaced. At least one of the conductive layers has a first doping segment having a first doping property and a second doping segment having a second doping property, the second doping property being different from the first doping property. The interface between the first doping segment and the second doping segment has a grain boundary.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括衬底和垂直形成在衬底上的堆叠结构。 层叠结构包括多个导电层和多个绝缘层，并且导电层和绝缘层交错。 导电层中的至少一个具有具有第一掺杂特性的第一掺杂区段和具有第二掺杂特性的第二掺杂区段，第二掺杂特性不同于第一掺杂特性。 第一掺杂段和第二掺杂段之间的界面具有晶界。