公开(公告)号：US06613657B1

公开(公告)日：2003-09-02

申请号：US10231133

申请日：2002-08-30

申请人： Minh Van Ngo ,  Dawn Hopper ,  Wenmei Li ,  Kelwin King Wai Ko ,  Kuo-Tung Chang ,  Tyagamohan Gottipati

发明人： Minh Van Ngo ,  Dawn Hopper ,  Wenmei Li ,  Kelwin King Wai Ko ,  Kuo-Tung Chang ,  Tyagamohan Gottipati

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 Å to 1,800 Å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 Å to 10,000 Å.

摘要翻译： 通过沉积BPSG，SA-CVD氧化物衬垫并将其流入底切区域，随后用P掺杂的HDP氧化物层填充间隙来补救由间隔物底切造成的器件泄漏。 实施方案包括在紧密间隔开的非易失性晶体管上沉积厚度为1,000至1,800的含有4至6重量％硼的BPSG，SA-CVD氧化物衬垫，并在沉积期间或之后加热以使BPSG流动， SA-CVD氧化物衬垫进入栅堆叠的侧壁间隔物的底切区域。 然后通过沉积厚度为6,000至10,000的P掺杂HDP层完成间隙填充。

公开(公告)号：US5824584A

公开(公告)日：1998-10-20

申请号：US876326

申请日：1997-06-16

申请人： Wei-Ming Chen ,  Lee Z. Wang ,  Kuo-Tung Chang ,  Craig Swift

发明人： Wei-Ming Chen ,  Lee Z. Wang ,  Kuo-Tung Chang ,  Craig Swift

IPC分类号： H01L21/8239 ,  H01L27/105 ,  H01L21/336

CPC分类号： H01L27/105 ,  H01L27/1052 ,  Y10S438/933

摘要： A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

摘要翻译： 示出了具有控制栅极（14）和侧壁选择栅极（28）的非易失性存储器。 侧壁选择栅极（28）与半导体掺杂氧化物（20）结合形成以形成非易失性存储单元（7）。 用于掺杂氧化物层（20）的半导体元件通常将包括硅或锗。 通过在掺杂氧化物（20）中存储电子来对非易失性存储单元（7）进行编程，并且使用带 - 带隧道进行擦除。

公开(公告)号：US5706228A

公开(公告)日：1998-01-06

申请号：US603939

申请日：1996-02-20

申请人： Kuo-Tung Chang ,  Craig A. Cavins ,  Ko-Min Chang ,  Bruce L. Morton ,  George L. Espinor

发明人： Kuo-Tung Chang ,  Craig A. Cavins ,  Ko-Min Chang ,  Bruce L. Morton ,  George L. Espinor

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C11/40

CPC分类号： G11C16/3427 ,  G11C16/0433 ,  G11C16/10

摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

摘要翻译： 具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。 存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。 为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。 为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。 为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗 在读操作期间。

公开(公告)号：US08183623B2

公开(公告)日：2012-05-22

申请号：US13075047

申请日：2011-03-29

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US07906807B2

公开(公告)日：2011-03-15

申请号：US12827069

申请日：2010-06-30

申请人： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  Kuo-Tung Chang ,  Huaqiang Wu

发明人： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  Kuo-Tung Chang ,  Huaqiang Wu

IPC分类号： H01L29/92 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。 与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

公开(公告)号：US07439141B2

公开(公告)日：2008-10-21

申请号：US10277395

申请日：2002-10-22

申请人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

发明人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

IPC分类号： H01L21/00

CPC分类号： H01L21/76235

摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

摘要翻译： 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。 该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

公开(公告)号：US20070026675A1

公开(公告)日：2007-02-01

申请号：US11193409

申请日：2005-08-01

申请人： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

发明人： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC分类号： H01L21/302

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。

公开(公告)号：US07029975B1

公开(公告)日：2006-04-18

申请号：US10839561

申请日：2004-05-04

申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/513

摘要： A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.

摘要翻译： 公开了一种用于耦合到源极线的方法和装置。 描述了具有排列成行和列的存储单元阵列的半导体结构。 存储单元阵列包括源区域，其注入在相邻的一对不相交的STI区域之间隔离并在植入期间与漏区隔离的n型掺杂剂。 源极触点沿着一排漏极触点排列，其被连接到一行存储器单元的漏极区域，并且源极触点耦合到源极区域以提供与多个源极线的电耦合。 在植入期间将注入的源极区域与漏极区域隔离使得能够将源极接触耦合到源极线，同时保持STI区域之间的n型掺杂剂并且避免横向扩散到位线。

公开(公告)号：US20060035431A1

公开(公告)日：2006-02-16

申请号：US10915771

申请日：2004-08-11

申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Zhigang Wang

发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66825

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.

摘要翻译： 根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。 该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。 该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。 根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。