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    ACCESS LINE MANAGEMENT IN A MEMORY DEVICE
    51.
    发明申请
    ACCESS LINE MANAGEMENT IN A MEMORY DEVICE 有权
    存储设备中的线路管理

    公开(公告)号：US20170076806A1

    公开(公告)日：2017-03-16

    申请号：US15342255

    申请日：2016-11-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

    Abstract translation: 存储器设备被配置为存储在对存储器设备中的特定行存储器单元执行的存储器件操作期间要应用的许多访问线偏置模式。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

    MICROELECTRONIC DEVICES HAVING A MEMORY ARRAY REGION AND A CONTROL LOGIC REGION
    58.
    发明申请
    MICROELECTRONIC DEVICES HAVING A MEMORY ARRAY REGION AND A CONTROL LOGIC REGION 有权

    公开(公告)号：US20230092320A1

    公开(公告)日：2023-03-23

    申请号：US18059165

    申请日：2022-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

    IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582

    Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
    59.
    发明申请
    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS 有权

    公开(公告)号：US20230039026A1

    公开(公告)日：2023-02-09

    申请号：US17396825

    申请日：2021-08-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

    BLOCK-ON-BLOCK MEMORY ARRAY ARCHITECTURE USING BI-DIRECTIONAL STAIRCASES
    60.
    发明申请
    BLOCK-ON-BLOCK MEMORY ARRAY ARCHITECTURE USING BI-DIRECTIONAL STAIRCASES 有权

    公开(公告)号：US20220238554A1

    公开(公告)日：2022-07-28

    申请号：US17720223

    申请日：2022-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Aaron S. Yip

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/08 ,  G11C11/56 ,  H01L21/768 ,  H01L21/3213 ,  G11C16/24

    Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

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