公开(公告)号：US20150054063A1

公开(公告)日：2015-02-26

申请号：US14517261

申请日：2014-10-17

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

公开(公告)号：US08878271B2

公开(公告)日：2014-11-04

申请号：US13782792

申请日：2013-03-01

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  G11C11/40

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

公开(公告)号：US12232311B2

公开(公告)日：2025-02-18

申请号：US18388769

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/40 ,  G11C11/4097 ,  H10B12/00 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

公开(公告)号：US20240373619A1

公开(公告)日：2024-11-07

申请号：US18662659

申请日：2024-05-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Srinivas Pulugurtha ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B12/00 ,  G11C11/402

Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

公开(公告)号：US11935960B2

公开(公告)日：2024-03-19

申请号：US17864244

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H10B12/00 ,  H10B53/20

CPC classification number: H01L29/78642 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7869 ,  H10B12/31 ,  H10B53/20

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

公开(公告)号：US11600535B2

公开(公告)日：2023-03-07

申请号：US16868133

申请日：2020-05-06

Applicant: Micron Technology, inc.

Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Yunfei Gao ,  Sanh D. Tang ,  Haitao Liu

IPC: H01L27/00 ,  H01L21/84 ,  H01L21/265 ,  H01L29/78 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11335775B2

公开(公告)日：2022-05-17

申请号：US16952774

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Jaydip Guha ,  Scott E. Sills ,  Yi Fang Lee

IPC: H01L29/10 ,  H01L27/06 ,  H01L27/108 ,  H01L29/24 ,  H01L21/8234 ,  H01L27/11502

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11088147B2

公开(公告)日：2021-08-10

申请号：US16453788

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Saurabh Keshav ,  Srinivas Pulugurtha ,  Mohd Kamran Akhtar ,  James B. Franek ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01L21/263 ,  H01L21/223

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

公开(公告)号：US20210125997A1

公开(公告)日：2021-04-29

申请号：US16666709

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Haitao Liu

IPC: H01L27/108 ,  H01L27/06

Abstract: Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10797135B2

公开(公告)日：2020-10-06

申请号：US16209495

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Yunfei Gao ,  Srinivas Pulugurtha

IPC: H01L29/788 ,  H01L29/08 ,  H01L27/108 ,  H01L21/8234 ,  H01L27/088

Abstract: An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.