APPARATUSES HAVING A VERTICAL MEMORY CELL
    51.
    发明申请
    APPARATUSES HAVING A VERTICAL MEMORY CELL 有权
    具有垂直存储单元的设备

    公开(公告)号:US20150054063A1

    公开(公告)日:2015-02-26

    申请号:US14517261

    申请日:2014-10-17

    Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

    Abstract translation: 用于向垂直存取装置提供身体连接的方法,装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线,沿着基板延伸到主体连接线接触柱的主体连接线,设置在主体连接线上的主体区域,设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括:将第一电压施加到身体连接线,以及向该字线施加第二电压,以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

    Vertical access device and apparatuses having a body connection line, and related method of operating the same
    52.
    发明授权
    Vertical access device and apparatuses having a body connection line, and related method of operating the same 有权
    具有主体连接线的垂直存取装置和装置及其操作方法

    公开(公告)号:US08878271B2

    公开(公告)日:2014-11-04

    申请号:US13782792

    申请日:2013-03-01

    Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

    Abstract translation: 用于向垂直存取装置提供身体连接的方法,装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线,沿着基板延伸到主体连接线接触柱的主体连接线,设置在主体连接线上的主体区域,设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括:将第一电压施加到身体连接线,以及向该字线施加第二电压,以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

    Memory device having 2-transistor vertical memory cell

    公开(公告)号:US12232311B2

    公开(公告)日:2025-02-18

    申请号:US18388769

    申请日:2023-11-10

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

    VERTICAL 2-TRANSISTOR MEMORY CELL
    54.
    发明申请

    公开(公告)号:US20240373619A1

    公开(公告)日:2024-11-07

    申请号:US18662659

    申请日:2024-05-13

    Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

    Integrated assemblies
    55.
    发明授权

    公开(公告)号:US11935960B2

    公开(公告)日:2024-03-19

    申请号:US17864244

    申请日:2022-07-13

    Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

    Integrated Assemblies, and Methods of Forming Integrated Assemblies

    公开(公告)号:US20210125997A1

    公开(公告)日:2021-04-29

    申请号:US16666709

    申请日:2019-10-29

    Abstract: Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

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