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    CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS
    51.
    发明公开
    CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20240178170A1

    公开(公告)日：2024-05-30

    申请号：US18401099

    申请日：2023-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou

    IPC: H01L23/00

    CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/0219 ,  H01L2224/03821 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

    Abstract: Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

    BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING
    56.
    发明申请
    BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING 有权

    公开(公告)号：US20210175194A1

    公开(公告)日：2021-06-10

    申请号：US17174827

    申请日：2021-02-12

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

    Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

    Methods of making semiconductor devices
    57.
    发明授权
    Methods of making semiconductor devices 有权

    公开(公告)号：US10734370B2

    公开(公告)日：2020-08-04

    申请号：US16396235

    申请日：2019-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Zhaohui Ma ,  Wei Zhou ,  Chee Chung So ,  Soo Loo Ang ,  Aibin Yu

    IPC: H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L21/683 ,  H01L21/78

    Abstract: Methods of making semiconductor device packages may involve cutting kerfs in streets between regions of a semiconductor wafer and positioning stacks of semiconductor dice on portions of surfaces of at least some adjacent regions. A protective material may be dispensed only between the stacks of the semiconductor dice, over the exposed remainders of the regions, and in the kerfs. A back side of the semiconductor wafer may be ground to a final thickness, revealing the protective material in the kerfs at a side of the semiconductor wafer opposite the stacks of the semiconductor dice. The protective material between the stacks of the semiconductor dice and within the kerfs may be cut through, leaving the protective material on sides of the semiconductor dice of the stacks and on side surfaces of the regions within the kerfs.

    METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES
    58.
    发明申请
    METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200211999A1

    公开(公告)日：2020-07-02

    申请号：US16236250

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

    Die Features for Self-Alignment During Die Bonding
    59.
    发明申请
    Die Features for Self-Alignment During Die Bonding 审中-公开

    公开(公告)号：US20200083178A1

    公开(公告)日：2020-03-12

    申请号：US16127769

    申请日：2018-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

    SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
    60.
    发明申请
    SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS 审中-公开

    公开(公告)号：US20190267352A1

    公开(公告)日：2019-08-29

    申请号：US16405935

    申请日：2019-05-07

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street

    IPC: H01L25/065 ,  H01L23/64 ,  H01L25/00 ,  H01L23/495 ,  H01L23/48

    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.

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