公开(公告)号：US10014311B2

公开(公告)日：2018-07-03

申请号：US15295577

申请日：2016-10-17

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A method of forming poly silicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first poly silicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US09893083B1

公开(公告)日：2018-02-13

申请号：US15293133

申请日：2016-10-13

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/06 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/033 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/7883

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US20170229470A1

公开(公告)日：2017-08-10

申请号：US15497009

申请日：2017-04-25

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

公开(公告)号：US11688808B2

公开(公告)日：2023-06-27

申请号：US17317674

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A. Khandekar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04 ,  H10B12/00

CPC classification number: H01L29/7841 ,  H01L21/02686 ,  H01L29/04 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/20

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US11621270B2

公开(公告)日：2023-04-04

申请号：US17385201

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US20220157837A1

公开(公告)日：2022-05-19

申请号：US17589310

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N, Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffrey B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L29/10

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20220093617A1

公开(公告)日：2022-03-24

申请号：US17027046

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L29/78 ,  H01L21/223 ,  H01L27/11597 ,  H01L27/1159 ,  H01L29/10 ,  H01L29/66

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20210265502A1

公开(公告)日：2021-08-26

申请号：US17317674

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A. Khandekar

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210265171A1

公开(公告)日：2021-08-26

申请号：US17318470

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US11094705B2

公开(公告)日：2021-08-17

申请号：US16518498

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.