公开(公告)号：US06879520B2

公开(公告)日：2005-04-12

申请号：US10601006

申请日：2003-06-20

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3418 ,  G11C2211/5643

摘要： A non-volatile semiconductor memory device includes: a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and a plurality of sense amplifier circuits configured to read data from the memory cell array, wherein each the sense amplifier circuit is configured to sense cell data of a first memory cell selected from the memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to the first memory cell and written after the first memory cell.

公开(公告)号：US20050030812A1

公开(公告)日：2005-02-10

申请号：US10935868

申请日：2004-09-08

申请人： Koji Hosono ,  Hiroshi Nakamura

发明人： Koji Hosono ,  Hiroshi Nakamura

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C16/0483

摘要： A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are connected to word lines, a first voltage generating circuit which generates a first voltage, a second voltage generating circuit which generates a second voltage using the first voltage, a word line selecting circuit which selects at least one of the word lines, a word line voltage supplying circuit which supplies the second voltage to the selected word line through the word line selecting circuit, and a transfer voltage supplying circuit which supplies the first voltage to the word line selecting circuit and stops supplying it to be in a floating state before transferring the second voltage from the word line voltage supplying circuit to the selected word line, in an operation in which the second voltage is supplied to the selected word line after the first voltage is supplied to the word line selecting circuit.

公开(公告)号：US06831859B2

公开(公告)日：2004-12-14

申请号：US10703503

申请日：2003-11-10

申请人： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

发明人： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC分类号： G11C1606

CPC分类号： G11C29/789 ,  G11C7/20 ,  G11C16/20 ,  G11C2029/4402

摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

摘要翻译： 非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。 存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。 非易失性半导体存储器还包括初始设置数据锁存器。 在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

公开(公告)号：US06690596B2

公开(公告)日：2004-02-10

申请号：US10303946

申请日：2002-11-26

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

IPC分类号： G11C506

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A semiconductor memory device comprising a memory cell array and a word-line select circuit. The memory cell array having first to third word lines connected to first to third groups of memory cells, respectively. The second word lines are adjacent to the first word lines. The word-line select circuit selects at least one row of memory cells. The word-line select circuit includes first to third groups of word-line select transistors arranged in row and column directions. The first to third groups of word-line select transistors are connected to the first to third word line, respectively. The third group of word-line select transistors are each arranged interposed between any adjacent two of the first and second group of word-line select transistors.

摘要翻译： 一种半导体存储器件，包括存储单元阵列和字线选择电路。 存储单元阵列具有分别连接到第一至第三组存储器单元的第一至第三字线。 第二字线与第一字线相邻。 字线选择电路选择至少一行存储单元。 字线选择电路包括以行和列方向布置的第一至第三组字线选择晶体管。 第一至第三组字线选择晶体管分别连接到第一至第三字线。 第三组字线选择晶体管分别布置在第一和第二组字线选择晶体管中的任何相邻的两个之间。

公开(公告)号：US06507508B2

公开(公告)日：2003-01-14

申请号：US09984960

申请日：2001-10-31

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

IPC分类号： G11C506

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A semiconductor memory device comprises a memory cell array, a block select circuit, a plurality of word-line-driving-signal lines, and a plurality of transfer transistors. The memory cell array includes a plurality of blocks, each of the blocks including memory cells arranged in rows and columns. The block select circuit selects one of the blocks of the memory cell array. The word-line-driving-signal lines receive voltages to be applied to a plurality of word lines in each block. The transfer transistors are connected between the word-line-driving-signal lines and the word lines of the memory cell array, and are controlled by outputs from the block select circuit. Any two of the transfer transistors, which correspond to each pair of adjacent ones of the word lines, are separate from each other lengthwise and widthwise, and one or more transfer transistors corresponding to another word line or other word lines are interposed therebetween.

公开(公告)号：US06462985B2

公开(公告)日：2002-10-08

申请号：US09731910

申请日：2000-12-08

申请人： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

发明人： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC分类号： G11C1606

CPC分类号： G11C29/789 ,  G11C7/20 ,  G11C16/20 ,  G11C2029/4402

摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

摘要翻译： 非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。 存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。 非易失性半导体存储器还包括初始设置数据锁存器。 在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

公开(公告)号：US09230665B2

公开(公告)日：2016-01-05

申请号：US13816799

申请日：2011-09-22

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： H01L27/115 ,  H01L21/8234 ,  H01L27/06 ,  G11C16/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3436 ,  H01L21/823487 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A control circuit provides an at least partially negative threshold voltage distribution to a memory cell, thereby erasing retained data of the memory cell, and provides multiple levels of positive threshold voltage distributions thereto, thereby programming multiple levels of data to the memory cell. The control circuit, when executing a program operation to the memory cell, executes a first program operation that provides the multiple levels of positive threshold voltage distributions to a first memory cell which is a memory cell subject to program, and executes a second program operation that provides a positive threshold voltage distribution, to a second memory cell adjacent to the first memory cell, irrespective of (regardless of) whether data to be programmed to the second memory cell is (already) present in the second memory cell or not.

摘要翻译： 控制电路向存储器单元提供至少部分负的阈值电压分布，从而擦除存储单元的保留数据，并向其提供多级的正阈值电压分布，从而将多级数据编程到存储单元。 控制电路在对存储器单元执行编程操作时，执行将第一程序操作提供给正在进行程序的存储器单元的第一存储单元，并且执行第二程序操作，该第一程序操作将正阈值电压分布提供多级， 提供与第一存储器单元相邻的第二存储单元的正阈值电压分布，而不管（不管）要被编程到第二存储器单元的数据是否已经存在于第二存储器单元中。

公开(公告)号：US08830751B2

公开(公告)日：2014-09-09

申请号：US13424812

申请日：2012-03-20

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C11/34 ,  H01L27/088 ,  G11C16/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/34 ,  H01L27/115 ,  H01L21/8234

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元，选择晶体管，存储器串，块和传输电路。 存储单元堆叠在半导体衬底上。 在存储器串中，存储单元和选择晶体管串联连接。 该块包括多个存储器串。 在数据写入和读取中，传送电路将正电压传送到与所选块中的选定存储器串相关联的选择栅极线，以及与所选块中未选择的存储器串相关联的选择栅极线的负电压，以及 到与未选择的块相关联的选择门线。

公开(公告)号：US08582345B2

公开(公告)日：2013-11-12

申请号：US13233738

申请日：2011-09-15

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C13/0002 ,  G11C2213/71

摘要： A nonvolatile semiconductor memory device comprises a three-dimensional cell array block in which a plurality of cell array layers are stacked, each of the cell array layers including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells disposed at each of intersections of the first and second lines and each including a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a reading control circuit for reading data from the memory cells under a condition set in respective groups to which one or more cell array layers having a common electric property of the memory cells belong.

摘要翻译： 非易失性半导体存储器件包括其中堆叠多个单元阵列层的三维单元阵列块，每个单元阵列层包括多个第一线，多条第二线被配置为与第一线相交，以及 设置在第一和第二线的每个交点处的多个存储单元，每个存储单元包括被配置为以非易失性方式存储作为数据的电可重写电阻值的可变电阻元件，以及用于从存储单元读取数据的读取控制电路 在设置在具有存储器单元的共同电特性的一个或多个单元阵列层所属的各个组中的条件下。

公开(公告)号：US08493770B2

公开(公告)日：2013-07-23

申请号：US12884965

申请日：2010-09-17

申请人： Koji Hosono ,  Yuri Terada ,  Takahiko Sasaki

发明人： Koji Hosono ,  Yuri Terada ,  Takahiko Sasaki

IPC分类号： G11C11/00

CPC分类号： G11C7/1015

摘要： A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring. The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.

摘要翻译： 半导体存储装置包括存储单元阵列，该存储单元阵列包括布置在第一布线和第二布线之间的相应交点处的存储单元。 每个存储单元包括串联连接的整流元件和可变电阻元件。 控制电路被配置为将第一电压施加到所选择的第一布线和低于第一电压的第二电压到所选择的第二布线，使得某一电位差被施加到位于所选择的第一布线之间的交叉点处的选定存储单元 接线和选定的第二个接线。 控制电路通过同时向多个第一布线施加第一电压来执行同时读取操作，以同时从多个存储单元执行读取操作。 可以在同时读取操作中同时切换要应用第一电压的第一布线的数量。