利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

142 条记录 (耗时 0.028 秒)

    Bus Termination System and Method
    53.
    发明申请
    Bus Termination System and Method 有权
    总线终端系统和方法

    公开(公告)号：US20100030934A1

    公开(公告)日：2010-02-04

    申请号：US12185472

    申请日：2008-08-04

    申请人： Michael Bruennert ,  Peter Gregorius ,  Georg Braun ,  Andreas Gaertner ,  Hermann Ruckerbauer ,  George Alexander ,  Johannes Stecker

    发明人： Michael Bruennert ,  Peter Gregorius ,  Georg Braun ,  Andreas Gaertner ,  Hermann Ruckerbauer ,  George Alexander ,  Johannes Stecker

    IPC分类号： G06F13/38 ,  G06F3/00

    CPC分类号： G06F13/4086

    摘要： A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

    摘要翻译： 存储器系统包括耦合到总线的多个集成电路芯片。 每个集成电路芯片具有耦合到总线的输入/输出节点，该输入/输出节点具有可编程的片上终端电阻器。 通过总线访问集成电路芯片之一的输入/输出节点。 每个集成电路芯片的可编程片上终端电阻独立地设置为终端电阻。 终端电阻由交易类型和正在被访问的多个存储器件中的哪一个确定，哪些信息可以通过单独的传输控制总线传输。

    Device for the production of standard-compliant signals
    54.
    发明授权
    Device for the production of standard-compliant signals 有权
    用于生产标准兼容信号的设备

    公开(公告)号：US07474876B2

    公开(公告)日：2009-01-06

    申请号：US10916776

    申请日：2004-08-12

    申请人： Jörg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

    发明人： Jörg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

    IPC分类号： H04B17/00 ,  H03C1/62

    CPC分类号： H04L27/368

    摘要： A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24). Moreover, the invention provides attenuating means (50) for attenuation of the signal dependent on the characteristics of the telecommunication channel.

    摘要翻译： 用于生产标准兼容信号（例如电信网络中的脉冲型信号）的装置用于以特定信号形式产生和适应和/或预失真信号，该特定信号形式取决于指定的标准信号形式 在一个标准。 该装置包括用于产生具有特定信号形式的信号的信号产生装置（10）和用于信号的自适应或预失真的信号调节装置（20）。 根据本发明的信号产生装置（10）通过使用可编程移位寄存器（14）进行数字实现，该可编程移位寄存器（14）包含用于与数字输入信号（1）相乘的标准信号形式指定的乘法器。 信号调节装置（20）包括数字滤波器（22）与下游多路复用器（24）的串行连接形式的基本上可伸缩的数字滤波器装置。 此外，本发明提供衰减装置（50），用于根据电信信道的特性衰减信号。

    Current mode digital data transmitter
    55.
    发明授权
    Current mode digital data transmitter 有权
    电流模式数字数据发送器

    公开(公告)号：US07450649B2

    公开(公告)日：2008-11-11

    申请号：US10481856

    申请日：2003-05-15

    申请人： Peter Gregorius ,  Armin Hanneberg

    发明人： Peter Gregorius ,  Armin Hanneberg

    IPC分类号： H04B3/00

    CPC分类号： H04L25/0266 ,  H04L25/085

    摘要： The invention relates to a transmitter for transmission of digital data via a transmission line (10), comprising a current-driving digital/analogue converter (1) which is arranged at the input of the transmitter; a current-operated form filter (2) for forming the current pulses which are supplied from the digital/analogue converter; a line driver (5) which carries out current/voltage conversion; and a circuit for offset compensation (6), which is arranged in a feedback path (11). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.

    摘要翻译： 本发明涉及一种用于经由传输线（10）传输数字数据的发射机，包括布置在发射机输入端的电流驱动数/模转换器（1） 用于形成从数字/模拟转换器提供的电流脉冲的电流操作形式滤波器（2） 执行电流/电压转换的线路驱动器（5）; 以及布置在反馈路径（11）中的偏移补偿电路（6）。 为了提高在发射机的输出端发送的脉冲的质量，本发明提出了在目前的基础上进行发射机的内部信号处理。

    Generating a sampling clock signal in a communication block of a memory device
    56.
    发明授权
    Generating a sampling clock signal in a communication block of a memory device 有权
    在存储器件的通信块中生成采样时钟信号

    公开(公告)号：US07269093B2

    公开(公告)日：2007-09-11

    申请号：US11264060

    申请日：2005-10-31

    申请人： Peter Gregorius ,  Martin Streibl

    发明人： Peter Gregorius ,  Martin Streibl

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/222

    摘要： A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a local clock signal having a predetermined phase relationship with respect to the input clock signal, and generating the sampling clock signal based on the local clock signal.

    摘要翻译： 一种方法在具有分布在存储器件中的多个通信块的存储器件的通信块中产生采样时钟信号。 该方法包括在通信块中接收输入时钟信号，仅响应于输入时钟信号产生相对于输入时钟信号具有预定相位关系的本地时钟信号，并且基于该时钟信号产生采样时钟信号 本地时钟信号。

    Method of transmitting data between different clock domains
    57.
    发明申请
    Method of transmitting data between different clock domains 审中-公开
    在不同时钟域之间传输数据的方法

    公开(公告)号：US20070208980A1

    公开(公告)日：2007-09-06

    申请号：US11343946

    申请日：2006-01-30

    申请人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

    发明人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

    IPC分类号： G01R31/28

    CPC分类号： G06F13/4059

    摘要： A method of transmitting data between different clock domains includes receiving data bits on the basis of a receiving clock, sequentially storing the data bits in a ring buffer, simultaneously transmitting a number of the stored data bits from the ring buffer on the basis of a first transmitting clock, and transmitting the stored data bits from the ring buffer on the basis of a second transmitting clock.

    摘要翻译： 一种在不同时钟域之间发送数据的方法包括：基于接收时钟接收数据比特，顺序地将数据比特存储在环形缓冲器中，同时基于第一 发送时钟，并且基于第二发送时钟从所述环形缓冲器发送所存储的数据比特。

    Timing recovery phase locked loop
    58.
    发明申请
    Timing recovery phase locked loop 审中-公开
    定时恢复锁相环

    公开(公告)号：US20070104292A1

    公开(公告)日：2007-05-10

    申请号：US11267930

    申请日：2005-11-04

    申请人： Peter Gregorius

    发明人： Peter Gregorius

    IPC分类号： H03D3/24

    CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/146 ,  H03L2207/50

    摘要： Methods and apparatus for timing recovery phase locked loops. One embodiment provides a phase detectors for generating phase difference signals on the basis of a received feedback signal and an input clock signal and an input data signal, respectively. A digital control unit is adapted to generate a control signal depending on the first and second phase difference signals A digitally controlled oscillator generates an output clock signal depending on the control signal. A feedback unit feeds the output clock signal to an input of the first phase detector as the feedback signal. And a data acquisition unit receives the data signal and the output clock signal of the digitally controlled oscillator to provide a data output signal synchronized to the output clock signal.

    摘要翻译： 用于定时恢复锁相环的方法和装置。 一个实施例提供了一种相位检测器，用于分别基于接收到的反馈信号和输入时钟信号和输入数据信号产生相位差信号。 数字控制单元适于根据第一和第二相位差信号产生控制信号。数字控制振荡器根据控制信号产生输出时钟信号。 反馈单元将输出时钟信号馈送到第一相位检测器的输入作为反馈信号。 并且数据采集单元接收数字信号和数字控制振荡器的输出时钟信号，以提供与输出时钟信号同步的数据输出信号。

    Semiconductor memory module and system
    59.
    发明申请
    Semiconductor memory module and system 失效
    半导体存储器模块和系统

    公开(公告)号：US20070025131A1

    公开(公告)日：2007-02-01

    申请号：US11192335

    申请日：2005-07-29

    申请人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    发明人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C5/06 ,  H05K1/142

    摘要： The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.

    摘要翻译： 本发明包括半导体存储器模块和使用其的半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。