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    Command-triggered on-die termination
    53.
    发明授权
    Command-triggered on-die termination 有权
    命令触发的片上终止

    公开(公告)号：US09135206B2

    公开(公告)日：2015-09-15

    申请号：US14560357

    申请日：2014-12-04

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

    IPC: H03K17/16 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  H03K19/00

    CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

    Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.

    Abstract translation: 集成电路装置向动态随机存取存储器（DRAM）发送指定DRAM内数字控制值的编程的一个或多个命令，数字控制值指示DRAM要耦合到DRAM的数据接口的终端阻抗 DRAM响应于接收到写入命令并且在接收与写入命令相对应的写入数据期间，并且DRAM在接收到与写入命令相对应的写入数据之后与数据接口分离。 此后，集成电路装置向DRAM发送指示在第一时间间隔期间通过DRAM的数据接口对写入数据进行采样的写入命令，并且使得DRAM在第一时间间隔期间将终止阻抗耦合到数据接口 时间间隔，并在第一个时间间隔后将数据接口的终端阻抗解耦。

    Error Correction In A Memory Device
    54.
    发明申请
    Error Correction In A Memory Device 有权
    存储器件中的错误校正

    公开(公告)号：US20150234707A1

    公开(公告)日：2015-08-20

    申请号：US14692092

    申请日：2015-04-21

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

    IPC: G06F11/10 ,  G11C29/44

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

    Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

    Error correction in a memory device
    55.
    发明授权
    Error correction in a memory device 有权
    存储器件中的错误校正

    公开(公告)号：US09037949B1

    公开(公告)日：2015-05-19

    申请号：US13846200

    申请日：2013-03-18

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

    Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

    Strobe Acquisition and Tracking
    56.
    发明申请
    Strobe Acquisition and Tracking 有权
    频闪采集跟踪

    公开(公告)号：US20140140149A1

    公开(公告)日：2014-05-22

    申请号：US13959633

    申请日：2013-08-05

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G11C7/22 ,  G11C7/02

    CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。

    Memory controller with staggered request signal output
    57.
    发明授权
    Memory controller with staggered request signal output 有权
    具有交错请求信号输出的存储控制器

    公开(公告)号：US08638637B2

    公开(公告)日：2014-01-28

    申请号：US13720720

    申请日：2012-12-19

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

    IPC: G11C8/00

    CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

    Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

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