公开(公告)号：US20160239208A1

公开(公告)日：2016-08-18

申请号：US15013032

申请日：2016-02-02

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt

IPC: G06F3/06

CPC classification number: G11C5/04 ,  G11C5/063 ,  G11C7/10 ,  G11C7/22

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

Abstract translation: 内存模块使用动态数据缓冲区为计算系统提供扩展容量。 存储器模块包括具有第一组数据引脚和第二组数据引脚的外部接口。 存储器模块包括第一组存储器芯片和第二组存储器芯片。 存储器模块包括用于控制第一组存储器芯片的第一注册时钟驱动器和用于控制第二组存储器芯片的第二注册时钟驱动器。 存储器模块还包括第一数据缓冲器，用于将第一组存储器芯片连接到第一组数据引脚;以及第二数据缓冲器，用于将第二组存储器芯片连接到第二组数据引脚。

公开(公告)号：US20150248926A1

公开(公告)日：2015-09-03

申请号：US14714722

申请日：2015-05-18

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US12136452B2

公开(公告)日：2024-11-05

申请号：US18209976

申请日：2023-06-14

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G06F1/08 ,  G06F3/06 ,  G06F5/06 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/409 ,  G11C29/02 ,  G11C11/4096

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US12062413B1

公开(公告)日：2024-08-13

申请号：US18234288

申请日：2023-08-15

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

公开(公告)号：US20240104036A1

公开(公告)日：2024-03-28

申请号：US18482268

申请日：2023-10-06

Applicant: Rambus Inc

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F13/287 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G06F2213/28

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20240095198A1

公开(公告)日：2024-03-21

申请号：US18480344

申请日：2023-10-03

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F13/1673 ,  G06F13/1678 ,  G06F13/4022 ,  G06F13/4265

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

公开(公告)号：US20240020249A1

公开(公告)日：2024-01-18

申请号：US18365696

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US11341070B2

公开(公告)日：2022-05-24

申请号：US17100560

申请日：2020-11-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  G11C5/02

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US11275702B2

公开(公告)日：2022-03-15

申请号：US17021024

申请日：2020-09-15

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

公开(公告)号：US11068161B1

公开(公告)日：2021-07-20

申请号：US15645596

申请日：2017-07-10

Applicant: Rambus Inc.

Inventor： Catherine Chen ,  Thomas J. Giovannini ,  John Eric Linstadt

IPC: G11C8/12 ,  G11C5/06 ,  G06F3/06 ,  G06F13/10 ,  G06F13/40

Abstract: In a memory module having a plurality of discrete memory die packages, an N-bit data interface and a command/address buffer, a memory access command and chip-select input signals are received within the command/address buffer. In response to the chip-select input signals, the command/address buffer outputs chip-select output signals greater in quantity than the chip-select input signals to exclusively enable one of a plurality of groups of the discrete memory die packages to respond to the memory access command, each of the plurality of groups of the discrete memory die packages having a collective data interface width less than the N-bit data interface width.