公开(公告)号：US06924180B2

公开(公告)日：2005-08-02

申请号：US10361934

申请日：2003-02-10

申请人： Elgin Quek

发明人： Elgin Quek

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/84

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconductor substrate not covered by the gate structure or by composite insulator spacers located on the sides of the gate structure. Selective removal of an overlying insulator component of the composite insulator spacer allows a subsequent pocket implant region to be formed in an area of the semiconductor substrate directly underlying a horizontal portion of a remaining L shaped insulator spacer component. The location of the pocket region, formed butting only the top portions of the sides of the heavily doped source/drain region, reduces the risk of punch through current while limiting the impact of junction capacitance.

摘要翻译： 已经开发了用于形成MOSFET器件的工艺，其特征在于仅与重掺杂源极/漏极区域的侧面的顶部附近放置的口袋区域。 该工艺的特征是在未被栅极结构覆盖的半导体衬底的区域中或通过位于栅极结构的侧面上的复合绝缘体间隔物形成重掺杂的源极/漏极区域。 选择性去除复合绝缘体间隔物的上覆绝缘体部件允许随后的口袋注入区域形成在半导体衬底的直接位于剩余的L形绝缘体间隔件部件的水平部分下方的区域中。 仅在重掺杂的源极/漏极区域形成对接的顶部的袋区域的位置降低穿通电流的风险，同时限制结电容的冲击。

公开(公告)号：US20050101102A1

公开(公告)日：2005-05-12

申请号：US10703289

申请日：2003-11-06

申请人： Tze Ho Chan ,  Weining Li ,  Elgin Quek ,  Jia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

发明人： Tze Ho Chan ,  Weining Li ,  Elgin Quek ,  Jia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76237 ,  H01L27/115 ,  H01L29/66825

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。 植入的源极区域形成在有源区域的一侧的沟槽中的一个中。 在有源区的另一侧的另一个沟槽中形成注入的漏极区。 然后在沟槽中形成浅沟槽隔离。 在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。

公开(公告)号：US09276041B2

公开(公告)日：2016-03-01

申请号：US13423793

申请日：2012-03-19

申请人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.

摘要翻译： 本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。 在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极 线和第二位线的可变电阻材料。

公开(公告)号：US09263132B2

公开(公告)日：2016-02-16

申请号：US13206780

申请日：2011-08-10

申请人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L21/336 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7881

摘要： A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

摘要翻译： 在存储器栅极堆叠和选择栅极之间制造具有鳍结构的分离栅极存储器单元。 实施例包括存储器栅极堆叠下方的第一沟道区域和选择栅极下方的第二沟道区域。

公开(公告)号：US09252270B2

公开(公告)日：2016-02-02

申请号：US13713393

申请日：2012-12-13

申请人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/7841 ,  H01L29/66545 ,  H01L29/78654

摘要： Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.

摘要翻译： 公开了具有更快编程和更低刷新率的浮体单元（FBC）的形成方法以及所得到的器件。 实施例包括在基板上形成绝缘体上硅（SOI）层; 形成围绕和/或在SOI层上的带工程层; 形成源极区域和漏极区域，所述源极区域和漏极区域中的至少一个在所述带状工程化层上; 以及在SOI层上，在源区和漏区之间形成栅极。

公开(公告)号：US08895402B2

公开(公告)日：2014-11-25

申请号：US13602310

申请日：2012-09-03

申请人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L21/20

CPC分类号： H01L45/1233 ,  H01L45/04 ,  H01L45/06 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1691

摘要： Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

摘要翻译： 公开了用于形成装置的存储装置和方法。 提供了制备具有与底部电极的较低电极电平的衬底。 鳍状堆叠层形成在下部电极层上。 垫片形成在翅片堆叠层的顶部。 间隔物的宽度小于光刻分辨率。 使用间隔件作为掩模来对翅片堆叠层进行图案化以形成翅片堆叠。 鳍片堆叠接触底部电极。 在衬底上形成层间电介质（ILD）层。 ILD层填充散热片堆叠周围的空间。 在ILD层上形成上电极层。 上电极电平具有与散热片堆叠接触的顶部电极。 电极和散热片堆叠形成鳍式存储单元。

公开(公告)号：US08785287B2

公开(公告)日：2014-07-22

申请号：US12803754

申请日：2010-07-06

申请人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

发明人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/7848

摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

摘要翻译： 制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。 以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。 在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。 结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

公开(公告)号：US08748271B2

公开(公告)日：2014-06-10

申请号：US13046313

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/772 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

公开(公告)号：US08492235B2

公开(公告)日：2013-07-23

申请号：US12980375

申请日：2010-12-29

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849

摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

公开(公告)号：US08446779B2

公开(公告)日：2013-05-21

申请号：US12583486

申请日：2009-08-21

申请人： Elgin Quek ,  Chunshan Yin ,  Shyue Seng Tan ,  Jae Gon Lee ,  Chung Foong Tan

发明人： Elgin Quek ,  Chunshan Yin ,  Shyue Seng Tan ,  Jae Gon Lee ,  Chung Foong Tan

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L29/42324 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42332

摘要： A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

摘要翻译： 非易失性存储器件包括具有金字塔形的硅纳米晶体作为电子存储元件的浮动栅极。 电子从金字塔形的硅纳米晶体通过栅极氧化层隧穿到非易失性存储器件的控制栅极。 每个硅纳米晶体的锥体形状在其峰值处集中电场以促进电子隧穿。 这允许擦除过程发生在比现有技术的器件更低的隧道电压和更短的隧道时间。