公开(公告)号：US08525289B2

公开(公告)日：2013-09-03

申请号：US13444955

申请日：2012-04-12

Applicant: Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

Inventor： Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

IPC: H01L23/58

CPC classification number: H01L21/823462 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract translation: 复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。 以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。 此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

公开(公告)号：US08445964B2

公开(公告)日：2013-05-21

申请号：US13349883

申请日：2012-01-13

Applicant: Rohit Pal ,  Stephan Waidmann

Inventor： Rohit Pal ,  Stephan Waidmann

IPC: H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract translation: 具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。 实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物 不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。 在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

公开(公告)号：US20130034942A1

公开(公告)日：2013-02-07

申请号：US13565970

申请日：2012-08-03

Applicant: Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

Inventor： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

Abstract translation: 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

公开(公告)号：US20120306027A1

公开(公告)日：2012-12-06

申请号：US13483630

申请日：2012-05-30

Applicant: Stephan-Detlef Kronholz ,  Rohit Pal ,  Gunda Beernink

Inventor： Stephan-Detlef Kronholz ,  Rohit Pal ,  Gunda Beernink

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.

Abstract translation: 当形成具有复杂的高k金属栅电极结构的晶体管和应变诱导半导体合金的复杂半导体器件时，可以通过在选择性外延生长工艺期间提供优异的生长条件来增强晶体管的均匀性和性能。 为此，可以在隔离区域保留半导体材料，以避免突出的肩部的形成。 此外，在一些说明性实施例中，为了避免不适当的材料损失，例如在去除电介质盖材料等时，实施附加机构。

公开(公告)号：US20120156864A1

公开(公告)日：2012-06-21

申请号：US13197387

申请日：2011-08-03

Applicant: Stephan Kronholz ,  Rohit Pal

Inventor： Stephan Kronholz ,  Rohit Pal

IPC: H01L21/8234

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.

Abstract translation: 当形成复杂的高k金属栅电极结构时，可以通过基于硬掩模方式生长阈值调节半导体合金来增强器件特性的均匀性，这可能导致不太显着的表面形貌，特别是在密集 包装设备区域。 为此，在一些说明性实施例中，沉积的硬掩模材料可用于选择性地提供厚度减小和均匀性优异的氧化物掩模。

公开(公告)号：US08198192B2

公开(公告)日：2012-06-12

申请号：US12775555

申请日：2010-05-07

Applicant: Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

Inventor： Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

IPC: H01L21/4763

CPC classification number: H01L21/823462 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract translation: 复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。 以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。 此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

公开(公告)号：US20120119308A1

公开(公告)日：2012-05-17

申请号：US13353013

申请日：2012-01-18

Applicant: Man Fai NG ,  Rohit Pal

Inventor： Man Fai NG ,  Rohit Pal

IPC: H01L29/772

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 包括金属栅电极的改进的半导体器件通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度而形成，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US20100096698A1

公开(公告)日：2010-04-22

申请号：US12644882

申请日：2009-12-22

Applicant: Igor Peidous ,  Rohit Pal

Inventor： Igor Peidous ,  Rohit Pal

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

Abstract: Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer

Abstract translation: 提供了应力增强型MOS晶体管。 提供一种半导体器件，其包括绝缘体上半导体结构，栅极绝缘体层，源极区域，漏极区域和覆盖栅极绝缘体层的导电栅极。 绝缘体上半导体结构包括：衬底，半导体层和设置在衬底和半导体层之间的绝缘层。 半导体层具有第一表面，第二表面和第一区域。 栅极绝缘体层覆盖第一区域，导电栅极覆盖栅极绝缘体层，源区域和漏极区域覆盖在第一表面上，并且包括应变诱导外延层

公开(公告)号：US20100055394A1

公开(公告)日：2010-03-04

申请号：US12551071

申请日：2009-08-31

Applicant: Zhishan Hua ,  Erdogan Gulari ,  Mark A. Burns ,  Rohit Pal ,  Onnop Srivannavit

Inventor： Zhishan Hua ,  Erdogan Gulari ,  Mark A. Burns ,  Rohit Pal ,  Onnop Srivannavit

IPC: B32B3/10 ,  B32B37/06

CPC classification number: F16K99/0032 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/50273 ,  B01L3/502738 ,  B01L3/502746 ,  B01L2300/0819 ,  B01L2400/0481 ,  B01L2400/0655 ,  B01L2400/0677 ,  F15B15/10 ,  F16K99/0044 ,  Y10T137/0391 ,  Y10T137/1624 ,  Y10T137/1812 ,  Y10T137/2142 ,  Y10T137/218 ,  Y10T137/2191 ,  Y10T137/2196 ,  Y10T137/2202 ,  Y10T137/2218 ,  Y10T428/23 ,  Y10T428/234 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24612

Abstract: A microactuator may be configured by activating a source of electromagnetic radiation to heat and melt a selected set of phase-change plugs embedded in a substrate of the microactuator, pressurizing a common pressure chamber adjacent to each of the plugs to deform the melted plugs, and deactivating the source of electromagnetic radiation to cool and solidify the melted plugs.

Abstract translation: 微致动器可以通过激活电磁辐射源来加热和熔化嵌入在微致动器的衬底中的一组相变插塞，对与每个插塞相邻的公共压力室进行加压以使熔化的插头变形，以及 停用电磁辐射源以冷却和固化熔化的塞子。

公开(公告)号：US20090228132A1

公开(公告)日：2009-09-10

申请号：US12045081

申请日：2008-03-10

Applicant: Kevin R. Lensing ,  Alok Vaid ,  Rohit Pal

Inventor： Kevin R. Lensing ,  Alok Vaid ,  Rohit Pal

IPC: G06F17/00

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method includes receiving a performance distribution for a plurality of devices to be fabricated in a semiconductor process flow. A performance target for a particular device is specified based on the performance distribution. A stressed material is formed in a recess adjacent a gate electrode of a transistor in the particular device in accordance with at least one operating recipe. The recess is spaced from the gate electrode by a gate proximity distance. A target value for the gate proximity distance is determined based on the performance target. At least one parameter of the operating recipe is determined based on the target value for the gate proximity distance.

Abstract translation: 一种方法包括接收要在半导体工艺流程中制造的多个器件的性能分布。 基于性能分布指定特定设备的性能目标。 根据至少一个操作配方，在与特定装置中的晶体管的栅电极相邻的凹部中形成应力材料。 凹槽与栅电极隔开一个栅极接近距离。 基于性能目标确定门接近距离的目标值。 基于门接近距离的目标值确定操作配方的至少一个参数。