公开(公告)号：US20180102152A1

公开(公告)日：2018-04-12

申请号：US15811576

申请日：2017-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G11C8/08 ,  G11C8/18 ,  G11C8/06 ,  G11C8/04 ,  G11C13/00

CPC classification number: G11C8/08 ,  G11C7/1018 ,  G11C8/04 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

公开(公告)号：US20180089087A1

公开(公告)日：2018-03-29

申请号：US15349949

申请日：2016-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Dongyan Jiang ,  Hongzhong Zheng

IPC: G06F12/0862 ,  G06F12/0868

CPC classification number: G06F12/0862 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/313 ,  G06F2212/6022 ,  G06F2212/6026

Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.

公开(公告)号：US20180046541A1

公开(公告)日：2018-02-15

申请号：US15286460

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US20170286005A1

公开(公告)日：2017-10-05

申请号：US15162517

申请日：2016-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F12/0864 ,  G06F12/0223 ,  G06F2212/1016 ,  G06F2212/1044

Abstract: A method of deduplicating memory in a memory module includes identifying a hash table array including hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying a plurality of virtual buckets each including some of the physical buckets, and each sharing at least one of the physical buckets with another of the virtual buckets, hashing a block of data according to a corresponding one of the hash functions to produce a hash value, determining whether an intended physical bucket has available space for the block of data according to the hash value, and determining whether a near-location physical bucket has available space for the block of data when the intended physical bucket does not have available space, the near-location physical bucket being in a same one of the virtual buckets as the intended physical bucket.

公开(公告)号：US20170256311A1

公开(公告)日：2017-09-07

申请号：US15227911

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G11C13/00

CPC classification number: G11C8/08 ,  G11C7/1018 ,  G11C8/04 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

公开(公告)号：US20170255398A1

公开(公告)日：2017-09-07

申请号：US15174761

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Benjamin Lim ,  Indong Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0632 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

公开(公告)号：US20170255390A1

公开(公告)日：2017-09-07

申请号：US15143248

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien Chang ,  Prasun Gera ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0605 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30196 ,  G06F15/785 ,  Y02D10/13

Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.

公开(公告)号：US20160140041A1

公开(公告)日：2016-05-19

申请号：US14725712

申请日：2015-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Hongzhong Zheng ,  Suhas ,  Krishna Malladi

IPC: G06F12/08

CPC classification number: G06F3/06 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0688 ,  G06F3/0689

Abstract: An electronic system includes: an interface block of a storage device configured to process system information from a system device; a memory block of the storage device, coupled to the interface block, partitioned by the interface block configured to process the system information for partitioning the memory block; and a storage block of a storage device, coupled to the memory block, configured to access a data block of the storage block provided to the system device.

Abstract translation: 电子系统包括：被配置为从系统设备处理系统信息的存储设备的接口块; 存储装置的存储块，耦合到所述接口块，由被配置为处理用于划分所述存储块的所述系统信息的所述接口块划分; 以及耦合到所述存储器块的存储设备的存储块，被配置为访问提供给所述系统设备的所述存储块的数据块。

公开(公告)号：US12032828B2

公开(公告)日：2024-07-09

申请号：US17713228

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04 ,  G11C11/40611 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20240211149A1

公开(公告)日：2024-06-27

申请号：US18593885

申请日：2024-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Shuangchen Li ,  Bob Brennan ,  Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F15/78 ,  G11C11/4096

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/067 ,  G06F15/7821 ,  G11C11/4096

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.