公开(公告)号：US09123632B2

公开(公告)日：2015-09-01

申请号：US13626346

申请日：2012-09-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/20 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/7869

Abstract: A highly reliable structure is provided when high-speed driving of a semiconductor device is achieved by improving on-state characteristics of the transistor. The on-state characteristics of the transistor are improved as follows: an end portion of a source electrode and an end portion of a drain electrode overlap with end portions of a gate electrode, and the gate electrode surely overlaps with a region serving as a channel formation region of an oxide semiconductor layer. Further, embedded conductive layers are formed in an insulating layer so that large contact areas are obtained between the embedded conductive layers and the source and drain electrodes; thus, the contact resistance of the transistor can be reduced. Prevention of coverage failure with a gate insulating layer enables the oxide semiconductor layer to be thin; thus, the transistor is miniaturized.

Abstract translation: 通过改善晶体管的导通状态特性来实现半导体器件的高速驱动时，提供高度可靠的结构。 晶体管的导通状态改善如下：源电极的端部和漏电极的端部与栅电极的端部重叠，并且栅极电极确定地与用作沟道的区域重叠 氧化物半导体层的形成区域。 此外，嵌入的导电层形成在绝缘层中，使得在嵌入的导电层和源极和漏极之间获得大的接触面积; 因此，可以降低晶体管的接触电阻。 利用栅极绝缘层防止覆盖失效，使氧化物半导体层变薄; 因此，晶体管小型化。

公开(公告)号：US09117662B2

公开(公告)日：2015-08-25

申请号：US14578578

申请日：2014-12-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsuo Isobe ,  Kunio Hosoya

IPC: H01L21/00 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/0237 ,  H01L21/02565 ,  H01L21/383 ,  H01L21/425 ,  H01L21/441 ,  H01L21/47573 ,  H01L27/10873 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/517 ,  H01L29/7869

Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.

Abstract translation: 为了提高包含氧化物半导体的晶体管的生产率，具有良好的电气特性。 在包括氧化物半导体膜上的栅绝缘膜和栅电极的顶栅晶体管中，在氧化物半导体膜上形成金属膜，向金属膜中添加氧以形成金属氧化物膜，并且金属氧化物 膜用作栅极绝缘膜。 在氧化物半导体膜上形成氧化物绝缘膜之后，可以在氧化物绝缘膜上形成金属膜。 向金属膜中添加氧以形成金属氧化物膜，并且还添加到氧化物半导体膜或氧化物绝缘膜。

公开(公告)号：US09112037B2

公开(公告)日：2015-08-18

申请号：US13758291

申请日：2013-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Yuki Hata ,  Suguru Hondo

IPC: H01L29/04 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.

Abstract translation: 提供一种包含氧化物半导体并具有良好操作特性的晶体管。 此外，通过使用晶体管，可以提供具有改善的操作特性的半导体。 在平面图中，晶体管的源极和漏极中的一个被环形栅电极包围。 此外，在平面图中，晶体管的源电极和漏电极之一被沟道形成区域包围。 因此，源电极通过在岛状氧化物半导体层的端部中产生的寄生沟道而不与漏电极电连接。

公开(公告)号：US20140269013A1

公开(公告)日：2014-09-18

申请号：US14208428

申请日：2014-03-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

IPC: G11C11/24

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US08637864B2

公开(公告)日：2014-01-28

申请号：US13632635

申请日：2012-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Saito ,  Atsuo Isobe ,  Kazuya Hanaoka ,  Junichi Koezuka ,  Shinya Sasagawa ,  Motomu Kurata ,  Akihiro Ishizuka

IPC: H01L29/12

CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

公开(公告)号：US20140003146A1

公开(公告)日：2014-01-02

申请号：US13923696

申请日：2013-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Atsuo Isobe ,  Yuji Iwaki ,  Koichiro Kamata ,  Yasuyuki Takahashi ,  Masumi Nomura

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G06F1/3203 ,  G06F1/3275 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/20 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit that consumes less power by stop of supply of power for a short time. In a storage element, before supply of power is stopped, data in a first storage circuit is stored to a second storage circuit, and the data is read from the second storage circuit and a verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. After supply of power is restarted, the data in the second storage circuit is stored to the first storage circuit, and the verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. In such a manner, verification can be performed without requiring a time for verification.

Abstract translation: 信号处理电路通过在短时间内停止供电而消耗较少的功率。 在存储元件中，在停止供电之前，将第一存储电路中的数据存储到第二存储电路，并且从第二存储电路读取数据，并且验证电路可以确定第二存储电路中的数据 存储电路与第一存储电路中的数据匹配。 在重新开始供电之后，第二存储电路中的数据被存储到第一存储电路，并且验证电路可以确定第二存储电路中的数据是否与第一存储电路中的数据匹配。 以这种方式，可以执行验证，而不需要验证时间。

公开(公告)号：US20130161611A1

公开(公告)日：2013-06-27

申请号：US13724974

申请日：2012-12-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Atsuo Isobe

IPC: H01L29/786 ,  H01L21/36

CPC classification number: H01L29/786 ,  H01L29/4908 ,  H01L29/7869

Abstract: Release of oxygen at a side surface of an island-shaped oxide semiconductor film is controlled and decrease in resistance is prevented. A semiconductor device includes an island-shaped oxide semiconductor film at least partly including a crystal, a first gate insulating film provided to cover at least a side surface of the island-shaped oxide semiconductor film, and a second gate insulating film provided to cover at least the island-shaped oxide semiconductor film and the first gate insulating film. The first gate insulating film is an insulating film that supplies oxygen to the island-shaped oxide semiconductor film, and the second gate insulating film is an insulating film which has a low oxygen-transmitting property

Abstract translation: 控制岛状氧化物半导体膜的侧面的氧的释放，防止电阻降低。 半导体器件包括至少部分地包括晶体的岛状氧化物半导体膜，设置成覆盖岛状氧化物半导体膜的至少侧面的第一栅极绝缘膜和设置成覆盖在岛状氧化物半导体膜上的第二栅极绝缘膜 至少岛状氧化物半导体膜和第一栅极绝缘膜。 第一栅极绝缘膜是向岛状氧化物半导体膜供给氧的绝缘膜，第二栅极绝缘膜是具有低透氧性的绝缘膜

公开(公告)号：US12057451B2

公开(公告)日：2024-08-06

申请号：US17845112

申请日：2022-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: G11C7/06 ,  G11C7/04 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US10825836B2

公开(公告)日：2020-11-03

申请号：US16657277

申请日：2019-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: H03K19/00 ,  H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US10453863B2

公开(公告)日：2019-10-22

申请号：US16208656

申请日：2018-12-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: H03K19/00 ,  H01L27/12 ,  H01L29/786 ,  G11C7/04 ,  H01L29/04 ,  H01L29/78 ,  H01L49/02 ,  H03K19/0185

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.