公开(公告)号：US20150076576A1

公开(公告)日：2015-03-19

申请号：US14552547

申请日：2014-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: H01L27/06

CPC classification number: H01L27/1255 ,  G02F1/134309 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/3413 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2310/0235 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/0629 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/78663 ,  H01L29/78672 ,  H01L29/7869

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Abstract translation: 本发明的目的是减少连接到电容器的晶体管的数量。 在结构中，包括电容器和一个晶体管，电容器的一个电极连接到布线，并且电容器的另一个电极连接到晶体管的栅极。 由于时钟信号被输入到布线，所以通过电容将时钟信号输入到晶体管的栅极。 然后，通过与时钟信号同步的信号来控制晶体管的导通/截止，从而重复晶体管导通的周期和晶体管截止的周期。 以这种方式，可以抑制晶体管的劣化。

公开(公告)号：US08941416B2

公开(公告)日：2015-01-27

申请号：US14222822

申请日：2014-03-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H03B1/00 ,  H03K3/00 ,  G09G3/14 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1255 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00 ,  H01L29/7869 ,  H03B1/00 ,  H03K3/00 ,  H03K17/6871

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract translation: 提供一种半导体器件，其特征在于晶体管数量减少的逆变器电路和移位寄存器电路。 半导体器件包括第一晶体管，第二晶体管和电容器。 第一晶体管的源极和漏极之一电连接到第一布线，另一个电连接到第二布线。 第二晶体管的源极和漏极之一电连接到第一布线，第二晶体管的栅极电连接到第一晶体管的栅极，第二晶体管的源极和漏极的另一个是 电连接到电容器的一个电极，而电容器的另一个电极电连接到第三布线。 第一和第二晶体管具有相同的导电类型。

公开(公告)号：US08890146B2

公开(公告)日：2014-11-18

申请号：US13763804

申请日：2013-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki ,  Shunpei Yamazaki

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/1334 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/13345 ,  G09G3/2007 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2330/021 ,  H01L21/823412 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/247 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

Abstract translation: 目的是提高半导体器件的驱动能力。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管的第一端子电连接到第一布线。 第一晶体管的第二端子电连接到第二布线。 第二晶体管的栅极电连接到第三布线。 第二晶体管的第一端子电连接到第三布线。 第二晶体管的第二端子电连接到第一晶体管的栅极。 在第一晶体管和第二晶体管的每一个中使用氧化物半导体层形成沟道区。 每个通道宽度为1μm的第一晶体管和第二晶体管的截止电流为1AA以下。

公开(公告)号：US20140327662A1

公开(公告)日：2014-11-06

申请号：US14335210

申请日：2014-07-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Ryo ARASAWA

IPC: G09G3/22

CPC classification number: G09G3/22 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0465 ,  G09G2300/0819 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/0264 ,  G09G2310/061

Abstract: The present invention is a method of driving a display device including a transistor, a capacitor one electrode of which is electrically connected to a first terminal of the transistor and the other electrode of which is electrically connected to a gate of the transistor, and a display element a first electrode of which is electrically connected to a second terminal of the transistor, including the steps of: electrically connecting the gate of the transistor, the first terminal of the transistor, and both electrodes of the capacitor to a first line in a first period; electrically connecting the gate of the transistor and the other electrode of the capacitor to a second line in a second period; and electrically connecting the first terminal of the transistor and one electrode of the capacitor to a third line in a third period.

Abstract translation: 本发明是一种驱动显示装置的方法，该显示装置包括晶体管，其电极的一个电极电连接到晶体管的第一端子，而另一个电极电连接到晶体管的栅极，显示器 元件，其第一电极电连接到晶体管的第二端子，包括以下步骤：将晶体管的栅极，晶体管的第一端子和电容器的两个电极电连接到第一线路中的第一线 期; 在第二周期中将晶体管的栅极和电容器的另一个电极电连接到第二线路; 以及在第三周期中将晶体管的第一端子和电容器的一个电极电连接到第三线路。

公开(公告)号：US08872299B2

公开(公告)日：2014-10-28

申请号：US13693208

申请日：2012-12-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/146 ,  G11C19/28 ,  G11C19/18 ,  H01L27/07 ,  G09G3/32

CPC classification number: H01L27/1255 ,  G09G3/3266 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/184 ,  G11C19/28 ,  H01L27/0733 ,  H01L27/124 ,  H01L27/1251

Abstract: A semiconductor device capable of high-speed operation. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is supplied with a first signal. One of a source and a drain of the second transistor is supplied with a first potential. A gate of the second transistor is supplied with a second signal. A first electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor. A second electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor. In a first period, the first signal is low and the second signal is high. In a second period, the first signal is high and the second signal is either low or high.

Abstract translation: 能够进行高速运转的半导体装置。 半导体器件包括第一晶体管，第二晶体管和电容器。 第一晶体管的源极和漏极之一被提供有第一信号。 第二晶体管的源极和漏极之一被提供有第一电位。 第二晶体管的栅极被提供有第二信号。 电容器的第一电极电连接到第一晶体管的源极和漏极中的另一个。 电容器的第二电极电连接到第二晶体管的源极和漏极中的另一个。 在第一时段中，第一信号为低，第二信号为高。 在第二时段中，第一信号为高，第二信号为低或高。

公开(公告)号：US20140118653A1

公开(公告)日：2014-05-01

申请号：US14147698

申请日：2014-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G02F1/1362 ,  H01L27/12

CPC classification number: G09G3/3233 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3659 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2320/0223 ,  G09G2320/043 ,  G09G2330/021

Abstract: There has been a problem that power consumption is increased if a potential of a signal line changes every time a video signal is applied to a driving transistor from the signal line, since the parasitic capacitance of the signal line stores and releases electric charges. In a configuration of a display portion provided with a gate signal line for selecting an input of a video signal to a pixel and a source signal line for inputting a video signal to the pixel, a switch is connected in series with the source signal line, the switch being controlled to be in on state when the pixel is not selected by the gate signal line, and in off state when the pixel is selected by the gate signal line. Accordingly, the parasitic capacitance of the source signal line which stores and releases electric charges affects only pixels between an output side of a source driver up to and including the pixel selected to be written with a video signal. Consequently, power consumed by the charging and discharging of the source signal line can be reduced, and thus low power consumption can be achieved.

Abstract translation: 如果信号线的寄生电容存储并释放电荷，则每当视频信号从信号线施加到驱动晶体管时信号线的电位发生变化，则存在功耗增加的问题。 在具有用于选择对像素的视频信号的输入的栅极信号线和用于向像素输入视频信号的源极信号线的显示部分的配置中，开关与源极信号线串联连接， 当栅极信号线没有选择像素时，开关被控制为处于导通状态，并且当栅极信号线选择像素时处于截止状态。 因此，存储和释放电荷的源极信号线的寄生电容仅影响源极驱动器的输出侧直到并且包括被选择用视频信号写入的像素的像素。 因此，可以减少源极信号线的充电和放电所消耗的功率，从而可以实现低功耗。

公开(公告)号：US20130278325A1

公开(公告)日：2013-10-24

申请号：US13921401

申请日：2013-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Atsushi Umezaki

IPC: H03K17/687

CPC classification number: G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  H01L27/0207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/687 ,  H03K19/0013 ,  H03K19/018557 ,  H03K19/018571

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

公开(公告)号：US20130249887A1

公开(公告)日：2013-09-26

申请号：US13849689

申请日：2013-03-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G09G5/00

CPC classification number: G09G5/001 ,  G09G3/3208 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/08 ,  G09G2300/0895 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3265 ,  H01L27/3276

Abstract: An object of the present invention is to provide a display device consuming lower amounts of power. The display device determines whether or not video signals corresponding to all of pixels in one row of a plurality of pixels are equal to one another. In a case where the video signals corresponding to at least two pixels among the video signals corresponding to all of the pixels in one row of the plurality of pixels, are different from each other, video signals input to an image signal input line are sequentially output to a plurality of source signal lines in synchronization with a sampling pulse output from a shift register. On the other hand, when the video signals corresponding to all of the pixels in one row of the plurality of pixels are equal to one another, input of a start pulse to the source driver is stopped, and the video signals input to the image signal input line are simultaneously output to the plurality of source signal line.

公开(公告)号：US20130223584A1

公开(公告)日：2013-08-29

申请号：US13775854

申请日：2013-02-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/28 ,  H01L27/088

CPC classification number: G11C19/28 ,  G09G3/2092 ,  G09G2310/0267 ,  G09G2310/0286 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/156 ,  H01L27/3244 ,  H01L29/7869

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

公开(公告)号：US12211569B2

公开(公告)日：2025-01-28

申请号：US18512287

申请日：2023-11-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G11C19/18 ,  G09G3/3266 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.