公开(公告)号：US20170186473A1

公开(公告)日：2017-06-29

申请号：US15390920

申请日：2016-12-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: G11C11/4074 ,  H01L27/108 ,  H01L29/786 ,  H01L27/115 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4074 ,  G11C5/146 ,  G11C5/147 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10805 ,  H01L27/115 ,  H01L28/00 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

公开(公告)号：US20170178752A1

公开(公告)日：2017-06-22

申请号：US15391929

申请日：2016-12-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Kazuaki OHSHIMA

IPC: G11C29/50 ,  H01L27/108 ,  G11C11/4096

CPC classification number: G11C29/50004 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/50016 ,  H01L27/108

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

公开(公告)号：US20170038826A1

公开(公告)日：2017-02-09

申请号：US15299579

申请日：2016-10-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuji NISHIJIMA ,  Hidetomo KOBAYASHI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract translation: 提供以低功耗模式工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路中的寄存器设置在与总线线路的接口中。 提供用于控制电源控制的电源门。 微控制器不仅可以在所有电路都有效的正常工作模式下工作，而且还可以在一些电路处于活动状态的低功耗模式下工作。 在诸如CPU的寄存器的寄存器中提供易失性存储器和非易失性存储器。 在电源停止之前，易失性存储器中的数据被备份在非易失性存储器中。 在操作模式返回到正常模式的情况下，当再次开始供电时，非易失性存储器中的数据被写回到易失性存储器中。

公开(公告)号：US20160351576A1

公开(公告)日：2016-12-01

申请号：US15159021

申请日：2016-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoaki ATSUMI ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/24 ,  H01L29/10

CPC classification number: H01L27/1157 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11573 ,  H01L27/11582

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

Abstract translation: 提供了高度集成的半导体器件。 半导体器件包括衬底，棱镜状绝缘体，包括串联连接的多个晶体管的存储单元串。 棱镜状绝缘体设置在基板上。 存储单元串设置在棱柱状绝缘体的侧面上。 多个晶体管各自包括栅极绝缘体和栅电极。 栅极绝缘体包括第一绝缘体，第二绝缘体和电荷累积层。 电荷累积层位于第一绝缘体和第二绝缘体之间。

公开(公告)号：US20160332493A1

公开(公告)日：2016-11-17

申请号：US15149324

申请日：2016-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Masayuki SAKAKURA ,  Kazuaki OHSHIMA

IPC: B60C23/04

CPC classification number: B60C23/0452 ,  B60C23/009 ,  B60C23/0454 ,  H01L29/7869

Abstract: To provide a circuit with low power consumption, a semiconductor device with low power consumption, a highly reliable semiconductor device, a tire whose performance is controlled, a moving object whose performance is controlled, or a moving object with a high degree of safety. A tire provided with a semiconductor device is provided. The semiconductor device includes a circuit portion, an antenna, and a sensor element. The circuit portion includes a transistor. The transistor includes an oxide semiconductor. The sensor element is configured to measure the air pressure of the tire.

Abstract translation: 为了提供具有低功耗的电路，具有低功耗的半导体器件，高可靠性半导体器件，其性能被控制的轮胎，其性能被控制的移动物体或具有高度安全性的移动物体。 提供了设置有半导体器件的轮胎。 半导体器件包括电路部分，天线和传感器元件。 电路部分包括晶体管。 晶体管包括氧化物半导体。 传感器元件被配置成测量轮胎的气压。

公开(公告)号：US20150381036A1

公开(公告)日：2015-12-31

申请号：US14842905

申请日：2015-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazunori WATANABE ,  Tomoaki ATSUMI

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M3/073

Abstract: Efficiency of a charge pump circuit is increased. The charge pump circuit includes serially connected fundamental circuits each including a diode-connected transistor and a capacitor. At least one transistor is provided with a back gate, and the back gate is connected to any node in the charge pump circuit. For example, the charge pump circuit is of a step-up type; in which case, if the transistor is an n-channel transistor, a back gate of the transistor in the last stage is connected to an output node of the charge pump circuit. Back gates of the transistors in the other stages are connected to an input node of the charge pump circuit. In this way, the voltage holding capability of the fundamental circuit in the last stage is increased, and the conversion efficiency can be increased because an increase in the threshold of the transistors in the other stages is prevented.

公开(公告)号：US20150340379A1

公开(公告)日：2015-11-26

申请号：US14816440

申请日：2015-08-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinori IEDA ,  Atsuo ISOBE ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L29/423 ,  H01L27/092 ,  H01L29/16 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L27/1207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/40 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/7869

Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

Abstract translation: 提供具有低功耗并且可以高速运行的半导体器件。 半导体器件包括：存储元件，其包括在沟道形成区域中包括晶体硅的第一晶体管，用于存储存储元件的数据的电容器;以及第二晶体管，其是用于控制电荷的供应，存储和释放的开关元件 电容器。 第二晶体管设置在覆盖第一晶体管的绝缘膜上。 第一和第二晶体管共同地具有源电极或漏电极。

公开(公告)号：US20150294990A1

公开(公告)日：2015-10-15

申请号：US14679104

申请日：2015-04-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoaki ATSUMI ,  Yuta ENDO

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1255 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

Abstract: A highly integrated semiconductor device is provided. A first region of a first semiconductor and a first region of a second semiconductor overlap each other. A first region of the first conductor and the first region of the first semiconductor overlap each other with a first insulator interposed therebetween. A first region of a second conductor and the first region of the second semiconductor overlap each other with a second insulator interposed therebetween. A first region of a third conductor is in contact with a second region of the first semiconductor. A second region of the third conductor is in contact with a second region of the second semiconductor. A first region of a fourth conductor is in contact with a second region of the first conductor. A second region of the fourth conductor is in contact with a second region of the second conductor.

Abstract translation: 提供了高度集成的半导体器件。 第一半导体的第一区域和第二半导体的第一区域彼此重叠。 第一导体的第一区域和第一半导体的第一区域彼此重叠，并且第一绝缘体插入其间。 第二导体的第一区域和第二半导体的第一区域彼此重叠，并且间隔开第二绝缘体。 第三导体的第一区域与第一半导体的第二区域接触。 第三导体的第二区域与第二半导体的第二区域接触。 第四导体的第一区域与第一导体的第二区域接触。 第四导体的第二区域与第二导体的第二区域接触。

公开(公告)号：US20150263007A1

公开(公告)日：2015-09-17

申请号：US14645566

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Yutaka OKAZAKI ,  Suguru HONDO

IPC: H01L27/105 ,  H01L29/04 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

Abstract translation: 提供一种具有良好电特性的晶体管的半导体器件。 半导体器件具有位于相同衬底上的存储器电路和电路。 存储电路包括电容器，第一晶体管和第二晶体管。 第一晶体管的栅极电连接到电容器和第二晶体管的源极和漏极之一。 电路包括串联电连接的第三晶体管和第四晶体管。 第一晶体管和第三晶体管各自包括含有硅的有源层，第二晶体管和第四晶体管各自包括包含氧化物半导体的有源层。

公开(公告)号：US20150214979A1

公开(公告)日：2015-07-30

申请号：US14679148

申请日：2015-04-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masafumi ITO ,  Tomoaki ATSUMI

IPC: H03M13/09

CPC classification number: H03M13/09 ,  H04B1/10

Abstract: An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

Abstract translation: 本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。 数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号 。