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    Three-dimensional semiconductor memory device
    52.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11664361B2

    公开(公告)日：2023-05-30

    申请号：US17577647

    申请日：2022-01-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

    IPC: H01L25/18 ,  H01L23/00

    CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

    MEMORY DEVICE FOR COLUMN REPAIR
    53.
    发明公开
    MEMORY DEVICE FOR COLUMN REPAIR 审中-公开

    公开(公告)号：US20230154559A1

    公开(公告)日：2023-05-18

    申请号：US18149302

    申请日：2023-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong PARK ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

    IPC: G11C29/00 ,  G11C16/04 ,  G11C29/44 ,  G06F11/20

    CPC classification number: G11C29/838 ,  G11C16/0483 ,  G11C29/44 ,  G06F11/2094 ,  G11C2029/1204

    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

    Memory device for column repair
    54.
    发明授权
    Memory device for column repair 有权

    公开(公告)号：US11574700B2

    公开(公告)日：2023-02-07

    申请号：US17245568

    申请日：2021-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong Park ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

    IPC: G11C29/00 ,  G06F11/20 ,  G11C16/04 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/12 ,  G11C29/02 ,  G11C29/52 ,  G11C29/42 ,  G11C29/24

    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

    Non-volatile memory device
    57.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US11348910B2

    公开(公告)日：2022-05-31

    申请号：US16863736

    申请日：2020-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanho Kim ,  Kyunghwa Yun ,  Daeseok Byeon

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

    Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

    Vertical capacitor structure and non-volatile memory device including the same
    59.
    发明授权
    Vertical capacitor structure and non-volatile memory device including the same 有权

    公开(公告)号：US11282851B2

    公开(公告)日：2022-03-22

    申请号：US16662073

    申请日：2019-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong Kwon ,  Chanho Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Chiweon Yoon

    IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/94 ,  H01L27/11582

    Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

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