公开(公告)号：US20220231131A1

公开(公告)日：2022-07-21

申请号：US17611933

申请日：2020-05-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Hitoshi KUNITAKE ,  Hajime KIMURA ,  Haruyuki BABA

IPC: H01L29/24 ,  H01L27/06 ,  H01L23/66

Abstract: A semiconductor device with low power consumption is provided. In a cascode circuit including a first transistor provided on a low power supply potential side and a second transistor provided on a high power supply potential side, a source or a drain of a third transistor and a capacitor are connected to a gate of the second transistor. A gate of the first transistor is electrically connected to a back gate of the second transistor. An OS transistor is used as the third transistor.

公开(公告)号：US20220223739A1

公开(公告)日：2022-07-14

申请号：US17712224

申请日：2022-04-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE

IPC: H01L29/786 ,  H01L27/108

Abstract: A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.

公开(公告)号：US20250151295A1

公开(公告)日：2025-05-08

申请号：US18838307

申请日：2023-02-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10B80/00 ,  H01L25/07 ,  H10B12/00 ,  H10D30/67

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor. The first memory cell and the second memory cell each include a transistor and a capacitor. One of a source and a drain of the transistor is electrically connected to a lower electrode of the capacitor. The first conductor includes a portion in contact with the other of the source and the drain of the transistor included in the first memory cell. A top surface of the first conductor includes a portion in contact with a bottom surface of the second conductor. The second conductor includes a portion in contact with the other of the source and the drain of the transistor included in the second memory cell.

公开(公告)号：US20250142803A1

公开(公告)日：2025-05-01

申请号：US19006634

申请日：2024-12-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Tatsuya ONUKI ,  Tomoaki ATSUMI ,  Kiyoshi KATO

IPC: H10B12/00 ,  G11C29/52 ,  H10D30/67

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

公开(公告)号：US20250107062A1

公开(公告)日：2025-03-27

申请号：US18832672

申请日：2023-01-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10B12/00 ,  G11C11/405 ,  G11C11/408

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening. The sixth conductor includes a region in contact with part of a top surface of the first conductor and part of a side surface of the first conductor in each of a plurality of layers.

公开(公告)号：US20250072009A1

公开(公告)日：2025-02-27

申请号：US18947085

申请日：2024-11-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO ,  Hiromichi GODO ,  Kazuki TSUDA ,  Hitoshi KUNITAKE

IPC: H10B63/00

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US20240395940A1

公开(公告)日：2024-11-28

申请号：US18664493

申请日：2024-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Fumito ISAKA ,  Yuichi SATO ,  Toshikazu OHNO ,  Hitoshi KUNITAKE ,  Tsutomu MURAKAWA

IPC: H01L29/786 ,  H01L29/66 ,  H10B12/00

Abstract: A transistor with high electrical characteristics is provided. A transistor with a high on-state current is provided. A transistor with small parasitic capacitance is provided. A transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated is provided. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer. A first insulating layer is between the first conductive layer and the second conductive layer. The second conductive layer is over the first insulating layer. The first insulating layer and the second conductive layer include an opening portion reaching the first conductive layer. The semiconductor layer is in contact with a sidewall of the opening portion. The semiconductor layer includes a first oxide layer and a second oxide layer. The first oxide layer includes a first region and a second region. The second oxide layer is between the first region and the second region.

公开(公告)号：US20240379866A1

公开(公告)日：2024-11-14

申请号：US18691097

申请日：2022-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Ryota HODO ,  Yasuhiro JINBO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Kunihiro FUKUSHIMA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor. The transistor includes an oxide, a first conductor and a second conductor that are over the oxide, a first insulator over the first conductor and the second conductor, a second insulator in an opening included in the first insulator, a third insulator over the second insulator, a fourth insulator over the third insulator, and a third conductor over the fourth insulator. The opening includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide with the second insulator, the third insulator, and the fourth insulator therebetween. The second insulator is in contact with a top surface of the oxide and a sidewall of the opening. The thickness of the second insulator is smaller than that of the third insulator. The fourth insulator is less permeable to oxygen than the third insulator is. The third conductor has a width greater than or equal to 3 nm and less than or equal to 15 nm in a cross-sectional view of the transistor in the channel length direction.

公开(公告)号：US20240313121A1

公开(公告)日：2024-09-19

申请号：US18575942

申请日：2022-07-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Satoru SAITO ,  Masahiro TAKAHASHI ,  Naoki OKUNO ,  Haruyuki BABA ,  Hitoshi KUNITAKE ,  Shunpei YAMAZAKI

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A semiconductor device with a small variation in transistor electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor, a second conductor, and a first insulator over the oxide; a second insulator over the first conductor and the second conductor; a third insulator over the first insulator; a third conductor over the third insulator; and a fourth insulator over the second insulator and the third conductor. The fourth insulator is in contact with a top surface of the second insulator and a top surface of the third conductor. The first insulator includes regions that are in contact with a top surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second insulator. The oxide includes indium, gallium, aluminum, and zinc. Each of the first insulator and the fourth insulator includes aluminum and oxygen. The fourth insulator has an amorphous structure. The oxide has a concentration gradient in which an aluminum concentration increases toward the top surface of the oxide from the bottom surface of the oxide.

公开(公告)号：US20230411521A1

公开(公告)日：2023-12-21

申请号：US18036727

申请日：2021-11-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki ITO ,  Hitoshi KUNITAKE ,  Kazuki TANEMURA

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L29/78391 ,  H01L29/7869 ,  H01L29/78648 ,  H01L29/4908 ,  G11C11/223

Abstract: A transistor having a large S value or a semiconductor device performing calculation utilizing a transistor operation in a subthreshold region is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a gate electrode including a region overlapping with the oxide semiconductor layer with an insulating layer therebetween, and a first conductive layer including a region overlapping with the oxide semiconductor layer with a ferroelectric layer therebetween. In particular, the ferroelectric layer includes a crystal having a crystal structure exhibiting ferroelectricity.