公开(公告)号：US20070272960A1

公开(公告)日：2007-11-29

申请号：US11890692

申请日：2007-08-07

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L29/76

CPC分类号： G11C11/22 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391

摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

摘要翻译： 本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。 导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。 通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。 消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。 还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

公开(公告)号：US20060180816A1

公开(公告)日：2006-08-17

申请号：US11058505

申请日：2005-02-14

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L29/26

CPC分类号： H05B33/145

摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.

摘要翻译： 提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。 通常，SRSO的Si浓度范围为5〜40％。 在一个方面，使用DC溅射工艺形成SRSO层。 另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。 同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。 响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。

公开(公告)号：US20060160335A1

公开(公告)日：2006-07-20

申请号：US11039463

申请日：2005-01-19

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/20

CPC分类号： C23C14/16 ,  C03C17/34 ,  C23C14/10 ,  C23C28/322 ,  C23C28/323 ,  C23C28/345 ,  C23C28/3455 ,  C23C28/42 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/31608 ,  H01L33/26

摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.

摘要翻译： 提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。 该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。 一方面，稀土元素和Si共溅射。 通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

公开(公告)号：US20060091107A1

公开(公告)日：2006-05-04

申请号：US10970885

申请日：2004-10-21

申请人： Tingkai Li ,  Bruce Ulrich ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Bruce Ulrich ,  David Evans ,  Sheng Hsu

IPC分类号： C03C25/68 ,  H01L21/302 ,  C23F1/00

CPC分类号： H01L29/6684 ,  C23F4/00 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32136

摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

摘要翻译： 选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO _{2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间的范围内; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压， 约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。}

公开(公告)号：US20060038242A1

公开(公告)日：2006-02-23

申请号：US10922712

申请日：2004-08-20

申请人： Sheng Hsu ,  Tingkai Li ,  Jong-Jan Lee

发明人： Sheng Hsu ,  Tingkai Li ,  Jong-Jan Lee

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/7869 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78621

摘要： The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2. The present invention ferroelectric transistor can be a metal-ferroelectric-semiconductive metal oxide FET having a gate stack of a top metal electrode disposed on a ferroelectric layer disposed on a semiconductive metal oxide channel on a substrate. Using additional layer of bottom electrode and gate dielectric, the present invention ferroelectric transistor can also be a metal-ferroelectric-metal (optional)-gate dielectric (optional)-semiconductive metal oxide FET.

摘要翻译： 本发明公开了一种采用半导体金属氧化物作为晶体管导电通道的新型晶体管结构。 通过用半导体金属氧化物沟道代替硅导电通道，晶体管可以实现更简单的制造工艺，并且可以实现3D结构以增加电路密度。 所公开的半导体金属氧化物晶体管可以在铁电非易失性存储器件中具有很大的潜力，具有与铁电材料良好的界面性质，与铁电层的可能的晶格匹配，减少或消除氧扩散问题以提高可靠性的另外的优点 铁电存储晶体管。 半导体金属氧化物膜优选是在晶体管工作条件下表现出半导体性质的金属氧化物，例如在二氧化铈或RuO 2 。 本发明的铁电晶体管可以是金属铁电半导体金属氧化物FET，其具有设置在设置在基板上的半导体金属氧化物沟道上的铁电层上的顶部金属电极的栅极堆叠。 使用附加的底部电极和栅极电介质层，本发明的铁电晶体管也可以是金属 - 铁电 - 金属（可选） - 门电介质（可选） - 导电金属氧化物FET。

公开(公告)号：US20060035390A1

公开(公告)日：2006-02-16

申请号：US11249883

申请日：2005-10-12

申请人： Tingkai Li ,  Sheng Hsu

发明人： Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/469

CPC分类号： H01L21/28273 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/56 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

公开(公告)号：US20050054166A1

公开(公告)日：2005-03-10

申请号：US10659547

申请日：2003-09-09

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L27/105 ,  G11C11/22 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L29/78

CPC分类号： G11C11/22 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391

摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

摘要翻译： 本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。 导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。 通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。 消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。 还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

公开(公告)号：US20080035946A1

公开(公告)日：2008-02-14

申请号：US11973525

申请日：2007-10-09

申请人： Wei Gao ,  Tingkai Li ,  Robert Barrowcliff ,  Yoshi Ono ,  Sheng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Robert Barrowcliff ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L33/00 ,  H01L23/58

CPC分类号： H05B33/145 ,  H01L21/3115 ,  H01L31/03046 ,  Y02E10/544

摘要： A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.

摘要翻译： 提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土（RE）元素掺杂硅（Si）氧化物膜的方法。 该方法包括：提供嵌入有第一稀土元素的Si的第一靶; 提供Si的第二个目标; 共溅射第一和第二个目标; 在掺杂有第一稀土元素的衬底上形成富Si氧化硅（SRSO）膜; 并对稀土元素掺杂的SRSO膜退火。 第一靶用铒（Er），镱（Yb），铈（Ce），镨（Pr）或铽（Tb）等稀土元素掺杂。 溅射功率在约75至300瓦（W）的范围内。 不同的溅射功率被应用于两个目标。 此外，可以通过改变两个目标的有效面积来控制沉积。 例如，其中一个目标可以被部分覆盖。

公开(公告)号：US20080006814A1

公开(公告)日：2008-01-10

申请号：US11900999

申请日：2007-09-15

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

摘要翻译： 提供金属/半导体/金属（MSM）二进制开关存储器件和制造工艺。 该器件包括存储器电阻器底部电极，存储器电阻器底部电极上方的存储器电阻器材料，以及存储器电阻器材料上的存储器电阻器顶部电极。 MSM底部电极覆盖存储电阻器顶部电极，半导体层覆盖在MSM底部电极上，并且MSM顶部电极覆盖半导体层。 MSM底部电极可以是诸如Pt，Ir，Au，Ag，TiN或Ti的材料。 MSM顶部电极可以是诸如Pt，Ir，Au，TiN，Ti或Al的材料。 半导体层可以是非晶Si，ZnO 2或InO 2。

公开(公告)号：US20080003697A1

公开(公告)日：2008-01-03

申请号：US11215521

申请日：2005-08-30

申请人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

发明人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich

IPC分类号： H01L21/00

CPC分类号： H01L21/28291 ,  H01L29/66583 ,  H01L29/78

摘要： A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

摘要翻译： 一种制造导电金属氧化物栅极铁电存储晶体管的方法，包括：在衬底上形成氧化物层并去除栅极区域中的氧化物层; 在氧化物层和暴露的栅极区上沉积导电金属氧化物层; 在所述金属氧化物层上沉积钛层; 图案化和蚀刻钛层和金属氧化物层以除去栅极区域之外的基板以除去钛层和金属氧化物层; 沉积，图案化和蚀刻氧化物层以形成栅极沟槽; 沉积和蚀刻阻挡绝缘体层以在栅极沟槽中形成侧壁势垒; 从栅极区域去除钛层; 沉积，平滑和退火栅极沟槽中的铁电层; 沉积，图案化和蚀刻顶部电极; 并完成导电金属氧化物栅极铁电存储晶体管。