公开(公告)号：US08168538B2

公开(公告)日：2012-05-01

申请号：US12472158

申请日：2009-05-26

申请人： Shih-Hung Chen ,  Tian-Jue Hong

发明人： Shih-Hung Chen ,  Tian-Jue Hong

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/101 ,  H01L21/743 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683

摘要： Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

摘要翻译： 本文描述了用于制造掩埋硅化物线的方法，以及高密度堆叠存储器结构。 如本文所述的用于制造集成电路的方法包括形成包括硅的半导体本体。 在半导体本体中形成多个沟槽以限定在相邻沟槽之间包括硅的半导体线，半导体线具有侧壁。 在沟槽内沉积硅化物前体以接触半导体管线的侧壁，并且去除硅化物前体的一部分以暴露侧壁的上部，并沿侧壁留下剩余的硅化物前体条。 然后通过引起硅化物条与半导体线的硅的反应形成硅化物导体。

公开(公告)号：US20120080716A1

公开(公告)日：2012-04-05

申请号：US13327171

申请日：2011-12-15

申请人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC分类号： H01L29/772

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US08097871B2

公开(公告)日：2012-01-17

申请号：US12433573

申请日：2009-04-30

申请人： Shih-Hung Chen ,  Yi-Chou Chen

发明人： Shih-Hung Chen ,  Yi-Chou Chen

IPC分类号： H01L47/00

CPC分类号： H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675 ,  Y10S977/943

摘要： Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

摘要翻译： 与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。 结果，相对于传统的蘑菇型存储单元，每单位电流值在横向边缘内产生的热量增加。 因此，引起相变所需的电流量减少。

公开(公告)号：US07804083B2

公开(公告)日：2010-09-28

申请号：US11940164

申请日：2007-11-14

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L47/00 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L45/143 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a bottom electrode, a thermal protect structure on the bottom electrode, and a multi-layer stack on the thermal protect structure. The thermal protect structure comprises a layer of thermal protect material, the thermal protect material having a thermal conductivity less than that of the bottom electrode material.

摘要翻译： 存储器件与制造方法一起被描述。 如本文所述的存储器件的实施例包括底部电极，底部电极上的热保护结构以及热保护结构上的多层堆叠。 热保护结构包括一层热保护材料，该热保护材料的热导率小于底部电极材料的热导率。

公开(公告)号：US07786460B2

公开(公告)日：2010-08-31

申请号：US11621390

申请日：2007-01-09

申请人： Hsiang Lan Lung ,  Shih-Hung Chen

发明人： Hsiang Lan Lung ,  Shih-Hung Chen

IPC分类号： H01L21/06 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1691

摘要： A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

摘要翻译： 相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于彼此之间并将电极的相对接触元件彼此电耦合的相变元件。 相变元件具有宽度，长度和厚度。 长度，厚度和宽度小于用于形成相变存储器单元的工艺的最小光刻特征尺寸。 可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变元件的长度和宽度都小于最小光刻特征尺寸。

公开(公告)号：US07692907B2

公开(公告)日：2010-04-06

申请号：US11717948

申请日：2007-03-13

申请人： Shih-Hung Chen ,  Ming-Dou Ker

发明人： Shih-Hung Chen ,  Ming-Dou Ker

IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： A circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs.

摘要翻译： 一种能够提供静电放电（ESD）保护的电路，所述电路包括包括第一高功率轨道和第一低功率轨道的第一组电力轨道，所述第一组电力轨道之间的第一接口电路，所述第一接口电路 具有至少一个栅电极，第一ESD器件，其包括耦合到所述第一接口电路的所述至少一个栅电极的端子，以及包括耦合到所述第一接口电路的所述至少一个栅电极的端子的第二ESD器件， 第一ESD器件和第二ESD器件被配置为当ESD发生时将第一接口电路的至少一个栅电极的电压电平保持在大致的接地电平。

公开(公告)号：US20090117763A1

公开(公告)日：2009-05-07

申请号：US12211062

申请日：2008-09-15

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01R13/44

CPC分类号： H05K5/0265 ,  H05K5/0282 ,  Y10S439/945

摘要： A card fixer is suitable to assist a card to be fixed in a slot of an electronic device. The card fixer includes a body and a clipping structure, wherein the body has a first side and a second side parallel to the first side. A hook is disposed on the first side of the body. The clipping structure extends out of the second side of the body for clipping the card thereon. When the clipping structure of the card fixer clips the card and the assembly of the card fixer with the card is inserted into the slot, the hook is locked on an inside wall of the slot.

摘要翻译： 卡固定器适合于帮助卡固定在电子设备的槽中。 卡定位器包括主体和夹持结构，其中主体具有平行于第一侧的第一侧和第二侧。 钩体设置在身体的第一侧。 剪辑结构从身体的第二侧延伸出来，以将卡夹在其上。 当卡片固定器的剪辑结构夹住卡时，卡片固定器与卡的组合被插入到插槽中，钩被锁定在插槽的内壁上。

公开(公告)号：US20090020746A1

公开(公告)日：2009-01-22

申请号：US12235773

申请日：2008-09-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US07414258B2

公开(公告)日：2008-08-19

申请号：US11424123

申请日：2006-06-14

申请人： Hsiang Lan Lung ,  Shih-Hung Chen

发明人： Hsiang Lan Lung ,  Shih-Hung Chen

IPC分类号： H01L29/18

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/31 ,  G11C2213/79 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

摘要： A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.

摘要翻译： 一种存储装置，包括具有顶侧的侧壁的第一盘形电极，具有顶侧的侧壁和在第一侧壁和第二侧壁之间的绝缘壁的第二盘形电极。 绝缘壁在相应顶面附近的第一和第二侧壁之间具有厚度。 记忆材料桥跨越绝缘壁，并且在绝缘壁之间限定第一和第二电极之间的电极间路径。 提供这样的存储单元阵列。 记忆材料的桥梁具有亚光刻尺寸。

公开(公告)号：US20080142984A1

公开(公告)日：2008-06-19

申请号：US11611428

申请日：2006-12-15

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L45/144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

摘要： An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the electrode layer stack, two sidewall conductor layers defining a second electrical current path. The ends of the sidewall conduction layers lie in the same planes as the electrode layer electrical contacts, such that electrode structure electrical contacts are each formed from one set of sidewall layer ends and an electrode layer electrical contact.

摘要翻译： 一种包括两个平行电路的电极结构。 多个电极层通常以叠片的形式形成在堆叠中，最外层提供电触点，并且限定穿过叠层的第一电流路径。 形成两个侧壁导体层以邻接电极层堆叠的任一端，限定第二电流路径的两个侧壁导体层。 侧壁导电层的端部位于与电极层电接触相同的平面中，使得电极结构电触头各自由一组侧壁层端部和电极层电接触形成。