公开(公告)号：US06878611B2

公开(公告)日：2005-04-12

申请号：US10336147

申请日：2003-01-02

申请人： Devendra K. Sadana ,  Stephen W. Bedell ,  Tze-Chiang Chen ,  Kwang Su Choe ,  Keith E. Fogel

发明人： Devendra K. Sadana ,  Stephen W. Bedell ,  Tze-Chiang Chen ,  Kwang Su Choe ,  Keith E. Fogel

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/36

CPC分类号： H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/823807 ,  Y10S438/96

摘要： In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.

摘要翻译： 在本发明的优选实施例中，描述了通过SiGe / SOI热混合工艺将图案化SOI区域转换为图案化SGOI（氧化硅上的硅 - 锗）的方法，以进一步增强嵌入式DRAM中逻辑电路的性能。 SGOI区域用作随后的Si生长的模板，使得Si被应变，并且Si中的电子和空穴具有较高的迁移率。

公开(公告)号：US06841457B2

公开(公告)日：2005-01-11

申请号：US10196611

申请日：2002-07-16

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L29/161 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/36

CPC分类号： H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

公开(公告)号：US06803240B1

公开(公告)日：2004-10-12

申请号：US10654231

申请日：2003-09-03

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21302

CPC分类号： G01N21/9501 ,  G01N21/9505 ,  G01N2021/8461

摘要： Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

摘要翻译： 这里描述了一种在SiGe合金层上描绘薄Si层中的晶体缺陷的方法。 该方法在Si中具有高缺陷选择性的缺陷蚀刻剂。 将Si蚀刻到允许缺陷凹坑到达下面的SiGe层的厚度。 然后使用可以与缺陷蚀刻剂相同或不同的第二蚀刻剂，其在凹陷下攻击SiGe层，同时保持Si完整。

公开(公告)号：US08853529B2

公开(公告)日：2014-10-07

申请号：US13568121

申请日：2012-08-06

申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Bahman Hekmatshoartabari ,  Ning Li ,  Devendra K. Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Bahman Hekmatshoartabari ,  Ning Li ,  Devendra K. Sadana ,  Davood Shahrjerdi

IPC分类号： H01L31/00 ,  H01L31/0687 ,  H01L31/0735 ,  H01L31/0304 ,  H01L31/18 ,  H01L21/02

CPC分类号： H01L31/06875 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02664 ,  H01L31/03042 ,  H01L31/0735 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

摘要： Solar cell structures include stacked layers in reverse order on a germanium substrate wherein a n++ (In)GaAs buffer layer plays dual roles as buffer and contact layers in the inverted structures. The absorbing layers employed in such exemplary structures are III-V layers such as (In)GaAs. Controlled spalling may be employed as part of the fabrication process for the solar cell structures, which may be single or multi-junction. The requirement for etching a buffer layer is eliminated, thereby facilitating the manufacturing process of devices using the disclosed structures.

摘要翻译： 太阳能电池结构在锗衬底上以相反的顺序包括堆叠层，其中n ++（In）GaAs缓冲层在倒置结构中起缓冲层和接触层的双重作用。 在这种示例性结构中采用的吸收层是III-V层，例如（In）GaAs。 受控的剥落可以用作太阳能电池结构的制造过程的一部分，其可以是单结或多结。 消除了蚀刻缓冲层的要求，从而便于使用公开的结构的器件的制造过程。

公开(公告)号：US08748296B2

公开(公告)日：2014-06-10

申请号：US13172793

申请日：2011-06-29

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

IPC分类号： H01L21/00

CPC分类号： H01L21/304 ,  C03C15/00 ,  C03C2218/34 ,  H01L31/1892

摘要： A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

摘要翻译： 使用边缘排除区域（其中应力层不存在（在沉积期间排除或随后除去）或存在但显着不附着于排除区域中的基底表面的边缘排除区域来最小化边缘相关底物断裂的方法 被提供。 在一个实施例中，该方法包括在基底基板的上表面和边缘附近形成边缘排除材料。 然后在基底基板的上表面和边缘排除材料的顶部的暴露部分上形成应力层，然后剥离位于应力层下方并且不被边缘排除材料覆盖的基底基板的一部分 。

公开(公告)号：US08709957B2

公开(公告)日：2014-04-29

申请号：US13481062

申请日：2012-05-25

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Ibrahim Alhomoudi

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/304 ,  B81C99/008 ,  H01L21/02002

摘要： A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.

摘要翻译： 利用位于基底的最上表面的一部分但不是全部的至少一个应力层部分剥离基底基板的局部区域的方法。 该方法包括提供具有均匀厚度的基底基底和跨越整个基底基底的平面最上表面。 至少一个具有形状的应力层部分形成在基底基板的最上表面的至少一部分但不是全部。 进行剥离，其从基底基板移除材料层部分并提供剩余的基底部分。 材料层部分具有至少一个应力层部分的形状，而剩余的基底部分具有位于其中的至少一个与至少一个应力层的形状相关的开口。

公开(公告)号：US08709914B2

公开(公告)日：2014-04-29

申请号：US13159893

申请日：2011-06-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/304 ,  H01L31/1896 ,  Y02E10/50 ,  Y02P80/30

摘要： A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.

摘要翻译： 提供了一种受控层转移的方法。 该方法包括向基底基底提供应力层。 应力层具有位于基底基板的上表面顶部的应力层，以及位于基底基板的每个侧壁边缘附近的自锁紧应力层。 然后将剥落抑制剂施加在基底衬底的应力层部分的顶部，然后将应力层的自锁定应力层部分与应力层部分分离。 位于应力层部分之下的基底部分的一部分然后从原始基底剥离。 剥落包括从应力层部分顶部置换剥落抑制剂。 剥落后，从基底基板的剥离部的顶部除去应力层。

公开(公告)号：US08679943B2

公开(公告)日：2014-03-25

申请号：US13215738

申请日：2011-08-23

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

IPC分类号： H01L21/30

CPC分类号： H01L21/30 ,  H01L31/1892 ,  Y02E10/50

摘要： A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

摘要翻译： 提供了一种剥落方法，其包括在基底表面上沉积应力层，并使应力层与平面转移接触。 然后，平面转移表面沿着平行于并且具有从基底基板的上表面垂直偏移的平面穿过。 平面转移表面在从基底基板的第一边缘到基底基板的相对的第二边缘的方向上穿过，以将基底基板切割并将基底基板的剥离部分转印到平面转印表面。 平面转移面沿着平面移动的平面与基底基板的上表面之间的垂直偏移是固定的距离。 垂直偏移的固定距离提供均匀的剥落力。 还提供了包括转印辊的剥落方法。

公开(公告)号：US08658444B2

公开(公告)日：2014-02-25

申请号：US13472584

申请日：2012-05-16

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/00

CPC分类号： H01L27/1218 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1266 ,  H01L2221/68368

摘要： A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility.

摘要翻译： 使用适用于柔性基板的技术制造高分辨率有源矩阵背板。 包含有源半导体器件的背板层形成在绝缘体上半导体衬底上。 背板层从基板剥离。 包括诸如LCD，OLED，感光材料或压电材料的无源器件的前端层形成在背板层上以形成有源矩阵结构。 可以制造有源矩阵结构以允许底部发射并提供机械灵活性。

公开(公告)号：US08642431B2

公开(公告)日：2014-02-04

申请号：US13437036

申请日：2012-04-02

申请人： Jee Hwan Kim ,  Stephen W. Bedell ,  Siegfried Maurer ,  Devendra K. Sadana

发明人： Jee Hwan Kim ,  Stephen W. Bedell ,  Siegfried Maurer ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  Y10S438/919

摘要： A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.

摘要翻译： 场效应晶体管（FET）具有在Ge中托管的通道。 FET通过选择性外延形成硅 - 锗（SiGe）源极和漏极。 SiGe源极和漏极在Ge沟道上施加拉伸应力。 在形成SiGe源极和漏极期间，n型掺杂物质和补偿物质被并入到SiGe源极和漏极中。 选择n型掺杂物种类和补偿种类，使得SiGe原子半径的尺寸在掺杂剂原子半径和补偿物质原子半径之间。