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    Memory Array Staircase Structure
    54.
    发明申请
    Memory Array Staircase Structure 有权

    公开(公告)号：US20220036931A1

    公开(公告)日：2022-02-03

    申请号：US17081380

    申请日：2020-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: G11C8/14 ,  H01L27/11597 ,  H01L27/105 ,  H01L21/822 ,  H01L21/8239

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

    SEMICONDUCTOR DEVICE, MEMORY ARRAY AND METHOD OF FORMING THE SAME
    57.
    发明申请
    SEMICONDUCTOR DEVICE, MEMORY ARRAY AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210375885A1

    公开(公告)日：2021-12-02

    申请号：US16886732

    申请日：2020-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin

    IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11578 ,  H01L23/522

    Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

    METHOD FOR FORMING A MFMIS MEMORY DEVICE
    58.
    发明申请
    METHOD FOR FORMING A MFMIS MEMORY DEVICE 有权

    公开(公告)号：US20210351191A1

    公开(公告)日：2021-11-11

    申请号：US16866727

    申请日：2020-05-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin

    IPC: H01L27/1159 ,  H01L27/11592 ,  H01L27/11595

    Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR
    59.
    发明申请
    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR 有权

    公开(公告)号：US20210343787A1

    公开(公告)日：2021-11-04

    申请号：US17078583

    申请日：2020-10-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC: H01L27/22 ,  H01L27/24

    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

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