公开(公告)号：US11329042B2

公开(公告)日：2022-05-10

申请号：US16678695

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Lien Jung Hung ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

公开(公告)号：US20210313144A1

公开(公告)日：2021-10-07

申请号：US16837724

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Meng ,  Chui-Ya Peng ,  Shih-Hao Lin

IPC: H01J37/317 ,  H01J37/08 ,  H01J37/32 ,  H01L21/265

Abstract: An ion implantation system including an ion implanter, a dopant source gas supply system and a monitoring system is provided. The ion implanter is inside a housing and includes an ion source unit. The dopant source gas supply system includes a first and a second dopant source gas storage cylinder in a gas cabinet outside of the housing and configured to supply a dopant source gas to the ion source unit, and a first and a second dopant source gas supply pipe coupled to respective first and second dopant source gas storage cylinders. Each of the first and second dopant source gas supply pipes includes an inner pipe and an outer pipe enclosing the inner pipe. The monitoring system is coupled to the outer pipe of each of the first and the second dopant source gas supply pipes.

公开(公告)号：US20210272966A1

公开(公告)日：2021-09-02

申请号：US17036487

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20210098305A1

公开(公告)日：2021-04-01

申请号：US16926528

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Cheng-Ting Ding ,  Chien-Chih Lin ,  Chien-Chih Lee ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Chih Chieh Yeh ,  Po-Kai Hsiao ,  Tsai-Yu Huang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US20200176447A1

公开(公告)日：2020-06-04

申请号：US16678695

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Lien Jung Hung ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

公开(公告)号：US12302609B2

公开(公告)日：2025-05-13

申请号：US18596115

申请日：2024-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L21/02 ,  H01L21/306 ,  H10B20/00 ,  H10B20/25 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

公开(公告)号：US20240395902A1

公开(公告)日：2024-11-28

申请号：US18791056

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chih Lin ,  Yen-Ting Chen ,  Wen-Kai Lin ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

公开(公告)号：US20240387274A1

公开(公告)日：2024-11-21

申请号：US18786886

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Tsai-Yu Huang ,  Chien-Chih Lin ,  Po-Kai Hsiao ,  Shih-Hao Lin ,  Chien-Chih Lee ,  Chih Chieh Yeh ,  Cheng-Ting Ding ,  Tsung-Hung Lee

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

公开(公告)号：US20240379851A1

公开(公告)日：2024-11-14

申请号：US18780748

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

公开(公告)号：US20240260249A1

公开(公告)日：2024-08-01

申请号：US18608199

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.