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    Field effect transistor having gate contact and source/drain contact separated by a gap
    54.
    发明授权
    Field effect transistor having gate contact and source/drain contact separated by a gap 有权

    公开(公告)号：US11637186B2

    公开(公告)日：2023-04-25

    申请号：US16406154

    申请日：2019-05-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

    Low-capacitance structures and processes
    55.
    发明授权
    Low-capacitance structures and processes 有权

    公开(公告)号：US11605736B2

    公开(公告)日：2023-03-14

    申请号：US17353089

    申请日：2021-06-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

    Interconnect structure with air-gaps
    57.
    发明授权
    Interconnect structure with air-gaps 有权

    公开(公告)号：US11495539B2

    公开(公告)日：2022-11-08

    申请号：US17144592

    申请日：2021-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.

    Semiconductor device with multi-layer dielectric
    58.
    发明授权
    Semiconductor device with multi-layer dielectric 有权

    公开(公告)号：US11476196B2

    公开(公告)日：2022-10-18

    申请号：US16597205

    申请日：2019-10-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L23/532 ,  H01L29/78 ,  H01L21/768 ,  H01L29/40 ,  H01L23/522 ,  H01L29/417

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

    Source/drain isolation structure and methods thereof
    60.
    发明授权
    Source/drain isolation structure and methods thereof 有权

    公开(公告)号：US11239106B2

    公开(公告)日：2022-02-01

    申请号：US16947932

    申请日：2020-08-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

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