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    Directional Patterning Methods
    51.
    发明申请
    Directional Patterning Methods 审中-公开

    公开(公告)号：US20180090370A1

    公开(公告)日：2018-03-29

    申请号：US15395310

    申请日：2016-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

    IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3115

    CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/31155

    Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

    Method to Reduce Etch Variation Using Ion Implantation
    55.
    发明申请
    Method to Reduce Etch Variation Using Ion Implantation 有权
    使用离子注入减少蚀刻变化的方法

    公开(公告)号：US20150187927A1

    公开(公告)日：2015-07-02

    申请号：US14175194

    申请日：2014-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

    IPC: H01L29/78 ,  H01L21/265

    CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

    Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

    COBALT FILL FOR GATE STRUCTURES
    56.
    发明公开
    COBALT FILL FOR GATE STRUCTURES 审中-公开

    公开(公告)号：US20240312837A1

    公开(公告)日：2024-09-19

    申请号：US18674066

    申请日：2024-05-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Ziwei Fang

    IPC: H01L21/768 ,  H01L21/02

    CPC classification number: H01L21/76877 ,  H01L21/02153 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/76816 ,  H01L21/76873

    Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

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