公开(公告)号：US08431480B2

公开(公告)日：2013-04-30

申请号：US13243882

申请日：2011-09-23

申请人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwaskai ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

发明人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwaskai ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76822 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

公开(公告)号：US20120015514A1

公开(公告)日：2012-01-19

申请号：US13243882

申请日：2011-09-23

申请人： JUNJI NOGUCHI ,  Takayushi Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwasaki ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

发明人： JUNJI NOGUCHI ,  Takayushi Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwasaki ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

IPC分类号： H01L21/768

CPC分类号： H01L21/76811 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76822 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

摘要翻译： 提高了布线的可靠性，其中包括以铜为主要成分的主导电膜。 在包括用作下层布线的布线的上表面的绝缘膜上形成由铜阻隔性优异的碳氮化硅膜形成的绝缘膜; 在绝缘膜上形成由与低介电常数材料膜具有优异粘合性的碳化硅膜形成的绝缘膜; 在绝缘膜上形成由作为层间绝缘膜的低介电常数材料形成的绝缘膜; 然后形成作为上层布线的布线。

公开(公告)号：US07948088B2

公开(公告)日：2011-05-24

申请号：US12063606

申请日：2006-08-25

申请人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

发明人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/763 ,  H01L21/76898 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L27/0203 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

摘要翻译： 为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得 从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量 使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生 导致膜或翘曲和晶片（W2）的裂纹被阻止。

公开(公告)号：US07777346B2

公开(公告)日：2010-08-17

申请号：US12345917

申请日：2008-12-30

申请人： Kensuke Ishikawa ,  Tatsuyuki Saito ,  Masanori Miyauchi ,  Toshio Saito ,  Hiroshi Ashihara

发明人： Kensuke Ishikawa ,  Tatsuyuki Saito ,  Masanori Miyauchi ,  Toshio Saito ,  Hiroshi Ashihara

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/2855 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.

摘要翻译： 在制造半导体集成电路器件时，在形成于半导体衬底上的第一级互连件上的层间绝缘膜中形成互连沟槽和接触孔，在沟槽和接触孔内部形成阻挡膜，使其膜 厚度从孔的底部的中心朝向接触孔底部的侧壁增加，在阻挡膜上形成铜膜，并且通过抛光形成第二级互连和连接器部分（插塞） 通过CMP。 以这种方式，通过连接器部分（插头）从第二级互连件流向第一级互连件的电流的几何最短路径与具有最低电阻的薄阻挡膜部分不一致，使得 电流路径可以分散，并且电子的浓度不容易发生。

公开(公告)号：US20090256261A1

公开(公告)日：2009-10-15

申请号：US12489006

申请日：2009-06-22

申请人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwasaki ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

发明人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwasaki ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

IPC分类号： H01L23/522

CPC分类号： H01L21/76811 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76822 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

摘要翻译： 提高了布线的可靠性，其中包括以铜为主要成分的主导电膜。 在包括用作下层布线的布线的上表面的绝缘膜上形成由铜阻隔性优异的碳氮化硅膜形成的绝缘膜; 在绝缘膜上形成由与低介电常数材料膜具有优异粘合性的碳化硅膜形成的绝缘膜; 在绝缘膜上形成由作为层间绝缘膜的低介电常数材料形成的绝缘膜; 然后形成作为上层布线的布线。

公开(公告)号：US20090115063A1

公开(公告)日：2009-05-07

申请号：US12345917

申请日：2008-12-30

申请人： Kensuke Ishikawa ,  Tatsuyuki Saito ,  Masanori Miyauchi ,  Toshio Saito ,  Hiroshi Ashihara

发明人： Kensuke Ishikawa ,  Tatsuyuki Saito ,  Masanori Miyauchi ,  Toshio Saito ,  Hiroshi Ashihara

IPC分类号： H01L23/52

CPC分类号： H01L21/2855 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.

摘要翻译： 在制造半导体集成电路器件时，在形成于半导体衬底上的第一级互连件上的层间绝缘膜中形成互连沟槽和接触孔，在沟槽和接触孔内部形成阻挡膜，使其膜 厚度从孔的底部的中心朝向接触孔底部的侧壁增加，在阻挡膜上形成铜膜，并且通过抛光形成第二级互连和连接器部分（插塞） 通过CMP。 以这种方式，通过连接器部分（插头）从第二级互连件流向第一级互连件的电流的几何最短路径与具有最低电阻的薄阻挡膜部分不一致，使得 电流路径可以分散，并且电子的浓度不容易发生。

公开(公告)号：US07387957B2

公开(公告)日：2008-06-17

申请号：US11058601

申请日：2005-02-16

申请人： Tatsuyuki Saito ,  Junji Noguchi ,  Hizuru Yamaguchi ,  Nobuo Owada

发明人： Tatsuyuki Saito ,  Junji Noguchi ,  Hizuru Yamaguchi ,  Nobuo Owada

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/48 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers formed, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

摘要翻译： 在半导体集成电路器件的制造工艺中，在实现由铝或铝合金构成的互连和由Cu或Cu合金制成的另一互连的连接时，在这些互连之间的接合部分处设置阻挡导体膜或插塞。 在形成的互连层中，最上面的一个由诸如铝或铝合金的布线材料制成，而下层由Cu或Cu合金制成。 最低的互连由不是Cu或Cu合金的导电材料制成。 例如，采用允许微小加工且具有低电阻和高电阻电阻（如钨）的导电材料。

公开(公告)号：US20080132059A1

公开(公告)日：2008-06-05

申请号：US11790760

申请日：2007-04-27

申请人： Junji Noguchi ,  Naohumi Ohashi ,  Tatsuyuki Saito

发明人： Junji Noguchi ,  Naohumi Ohashi ,  Tatsuyuki Saito

IPC分类号： H01L21/4763

CPC分类号： H01L21/0217 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/3212 ,  H01L21/67219 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

摘要翻译： 通过使用CMP的抛光来形成嵌入在氧化硅膜的互连槽中的Cu互连，以提高使用Damascene方法形成的铜互连的绝缘击穿电阻，并且在CMP后的清洗步骤中，氧化硅膜的表面 并且通过还原等离子体（氨等离子体）处理Cu互连。 随后，形成连续的盖膜（氮化硅膜）而没有真空断裂。

公开(公告)号：US06908847B2

公开(公告)日：2005-06-21

申请号：US10329831

申请日：2002-12-27

申请人： Tatsuyuki Saito ,  Naofumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

发明人： Tatsuyuki Saito ,  Naofumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

IPC分类号： H01L29/43 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/84 ,  H01L23/532 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.

摘要翻译： 半导体器件具有具有布线沟槽的第一层间绝缘膜; 布线部分，其具有形成在所述布线沟槽的侧壁和底表面上的第一阻挡金属层，形成在所述第一阻挡金属层上以嵌入所述布线沟槽的第一导体层和形成在所述第一导体层上的封盖阻挡金属膜 ; 第二层间绝缘膜，形成在所述第一层间绝缘膜上并具有连接孔; 以及连接部，其具有形成在所述连接孔的侧壁和下表面上的第二阻挡金属层，以及形成在所述第二阻挡金属层上以嵌入所述连接孔的第二导体层; 其中，在所述连接部分和所述布线部分之间的连接处，所述连接孔底面上的所述第二阻挡金属层和覆盖阻挡金属膜中的至少一个被去除。

公开(公告)号：US06861756B2

公开(公告)日：2005-03-01

申请号：US10797017

申请日：2004-03-11

申请人： Tatsuyuki Saito ,  Junji Noguchi ,  Hizuru Yamaguchi ,  Nobuo Owada

发明人： Tatsuyuki Saito ,  Junji Noguchi ,  Hizuru Yamaguchi ,  Nobuo Owada

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/48 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower, one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

摘要翻译： 在半导体集成电路器件中，在连接由铝或铝合金制成的互连以及由Cu或Cu合金制成的另一个互连时，在这些互连之间的接合部分处设置阻挡导体膜或插塞。 在互连层中，最上面的一个由诸如铝或铝合金的布线材料制成，而下层由Cu或Cu合金制成。 最低的互连由不是Cu或Cu合金的导电材料制成。 例如，采用允许微小加工且具有低电阻和高电阻电阻（如钨）的导电材料。