公开(公告)号：US06771535B2

公开(公告)日：2004-08-03

申请号：US10412423

申请日：2003-04-14

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

IPC分类号： G11C1100

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16

摘要： Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the-amplified current to an associated read data line.

摘要翻译： 公开了一种快速，高度集成和高可靠性的磁阻随机存取存储器（MRAM）和使用MRAM的半导体器件。 半导体器件使用存储单元执行MRAM的读出操作，用于通过使用具有高S / N比的磁性隧道结（MTJ）元件的磁阻的变化来存储信息。 每个存储单元包括MTJ元件和双极晶体管。 通过选择字线，通过双极晶体管放大在目标存储单元的MTJ元件中流动的电流并将放大的电流输出到相关联的读取数据线来执行读出操作。

公开(公告)号：US06683813B2

公开(公告)日：2004-01-27

申请号：US10315938

申请日：2002-12-11

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C702

CPC分类号： G11C11/4099 ,  G11C7/14

摘要： There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is comprised of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.

摘要翻译： 提供了用于读出具有放大能力的存储单元的操作的参考电压产生方法和虚拟单元。 存储单元包括读取NMOS晶体管，写入晶体管和耦合电容。 虚拟单元被制成使得两个存储单元串联连接。 每个数据线的最远端布置在相对于读出放大器的虚拟单元。 通过使存储单元的读取NMOS晶体管和虚设单元中的每一个中流动的电流量的差异来产生参考电压。 结果，可以实现与现有技术的装置相比显示更高速度，更高集成度和更低电力的DRAM。

公开(公告)号：US06335901B1

公开(公告)日：2002-01-01

申请号：US09531467

申请日：2000-03-20

申请人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

发明人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

摘要翻译： 响应于外部端子（OPT）的第一状态，SDRAM将其操作模式选择为SDR模式，从而释放已经从存储器读出的数据，以响应于由时钟产生的时钟信号 再生电路具有响应于外部端子（OPT）的第二状态而比较电路的输入和输出的相位或选择为DDR模式的功能，从而释放从 响应于与外部时钟信号同步的由时钟信号发生电路产生的时钟信号，存储器垫。

公开(公告)号：US06205086B1

公开(公告)日：2001-03-20

申请号：US09560724

申请日：2000-04-28

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).

摘要翻译： 相位控制电路包括分别向第一时钟信号（BDA1）分配不同的预定延迟时间的多个固定延迟电路（200-0至200-5）;接收从多个时钟信号输出的时钟信号的检测电路（201） 的固定延迟电路和与其中的第一时钟信号不同的第二时钟信号（PCLK），并产生以多个位表示的检测信号（202），每个位对应于第一时钟信号和第二时钟之间的相位差 信号和可变延迟电路（200-6），其将与每个检测到的信号相对应的相位差延迟到第三时钟信号（BDA2）。

公开(公告)号：US6166990A

公开(公告)日：2000-12-26

申请号：US332143

申请日：1999-06-14

申请人： Tsukasa Ooishi ,  Satoru Hanzawa ,  Kiyoshi Nakatsuka

发明人： Tsukasa Ooishi ,  Satoru Hanzawa ,  Kiyoshi Nakatsuka

IPC分类号： G11C11/413 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/417 ,  H01L21/822 ,  H01L27/04 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/4076

摘要： A frequency determination circuit generating a clock signal phase-locking with an external clock signal at a coarse precision and a fine adjust circuit generating an internal synchronizing signal phase-locking with the external clock signal at a fine precision are provided. The fine adjust circuit has a function of adjusting the phase of the frequency determination circuit when phase synchronization is to be carried out exceeding the adjust range thereof. The frequency determination circuit and the fine adjust circuit receive a clock power supply voltage. A clock reproduction circuit is provided which generates an internal clock signal phase-locking with an external clock signal or a reference clock signal stably even when the operating environment changes.

摘要翻译： 提供了以粗精度产生具有外部时钟信号的时钟信号相位锁定的频率确定电路和以外部时钟信号以精确的精度产生内部同步信号锁相的微调电路。 微调电路具有当要执行超过其调整范围的相位同步时调节频率确定电路的相位的功能。 频率确定电路和微调电路接收时钟电源电压。 提供了一种时钟再现电路，即使当操作环境改变时也能稳定地产生与外部时钟信号或参考时钟信号相位锁定的内部时钟信号。

公开(公告)号：US20130141968A1

公开(公告)日：2013-06-06

申请号：US13814104

申请日：2011-08-26

申请人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

发明人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

IPC分类号： G11C13/00

CPC分类号： G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

摘要翻译： 本发明的目的是提高相变存储器的重写传输速率和可靠性。 为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件 彼此完全设置，之后，与数据模式对应的单元的一部分被重置。 或者，执行相反的操作。

公开(公告)号：US08289764B2

公开(公告)日：2012-10-16

申请号：US13139297

申请日：2009-12-07

申请人： Satoru Hanzawa

发明人： Satoru Hanzawa

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C7/18 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

摘要： A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT0, MT1 are provided respectively at points of intersection of global bit line GBL0 and global word lines GWL00B, GWL01B. Word lines WL000 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD0 which is controlled by GWL00B, and word lines WL001 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD1 controlled by GWL01B. For example, when WD0 is activated in accordance with a rewrite operation, an output from WD0 is connected to GBL0 via any one of four memory cells MC00, MC01 connected to WL000 of MT0, MT1.

摘要翻译： 实现了高度可靠，高度集成的大容量相变存储器。 为此，例如，分别在全局位线GBL0和全局字线GWL00B，GWL01B的交点处提供存储器片MT0，MT1。 MT0，MT1的字线WL000通常连接到由GWL00B控制的字线驱动电路WD0的输出，MT0，MT1的字线WL001共同连接到控制了字线驱动电路WD1的输出 由GWL01B。 例如，当根据重写操作激活WD0时，WD0的输出通过连​​接到MT0，MT1的WL000的四个存储单元MC00，MC01中的任一个连接到GBL0。

公开(公告)号：US20120137058A1

公开(公告)日：2012-05-31

申请号：US13389260

申请日：2010-06-18

申请人： Satoru Hanzawa

发明人： Satoru Hanzawa

IPC分类号： G06F12/00

CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097

摘要： A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period.

摘要翻译： 实现了高速大容量相变存储器。 根据本发明的半导体器件包括：多个存储器平面MP; 与多个存储器平面配对的多个存储信息寄存器组SDRBK; 和芯片控制电路CPCTL。 多个存储器平面包括多个存储单元。 此外，多个存储信息寄存器组临时保留要存储在多个存储器平面中的信息。 此外，芯片控制电路包括临时存储指示存储信息的卷的值的寄存器，并且第一存储信息量小于第二存储信息量。 当第一存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第一时段期间被激活。 当第二存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第二时段期间被激活。 通过这种结构，第一周期比第二周期短。

公开(公告)号：US20110283039A1

公开(公告)日：2011-11-17

申请号：US13191442

申请日：2011-07-26

申请人： MOTOYASU TERAO ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

发明人： MOTOYASU TERAO ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

IPC分类号： G06F12/06

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

公开(公告)号：US20110273927A1

公开(公告)日：2011-11-10

申请号：US13104005

申请日：2011-05-09

申请人： Satoru Hanzawa ,  Yoshitska Sasago

发明人： Satoru Hanzawa ,  Yoshitska Sasago

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  H01L27/2454 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).

摘要翻译： 半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。 存储单元组各自具有串联连接的第一和第二存储器单元。 第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储装置。 第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。 用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组 阵列MA）。