公开(公告)号：US20060232316A1

公开(公告)日：2006-10-19

申请号：US10565190

申请日：2004-07-15

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： G06F1/04

CPC分类号： G06F1/324 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3296 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00032 ,  H03K2005/00045 ,  H03K2005/0013 ,  Y02D10/126 ,  Y02D10/172

摘要： In a multi-supply-voltage semiconductor device including multiple blocks 31, 32, each of which has independent clock circuit 41, 42, and operating with variable power supply 101, variable delay circuit 20 which changes the amount of delay in accordance with the voltage value of the variable power supply 101 is provided to a clock signal supplied to several blocks 32 from clock generator circuit 10. This can reduce clock skew between the blocks even when the power supply voltage of variable power supply 101 is changed.

摘要翻译： 在包括多个块31,32的多电源电压半导体器件中，每个具有独立的时钟电路41,42，并且与可变电源101一起工作，可变延迟电路20根据电压来改变延迟量 可变电源101的值被提供给从时钟发生器电路10提供给多个块32的时钟信号。 这可以减少块之间的时钟偏移，即使可变电源101的电源电压改变。

公开(公告)号：US20060091936A1

公开(公告)日：2006-05-04

申请号：US11261753

申请日：2005-10-31

申请人： Yoshifumi Ikenaga ,  Koichi Takeda ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Koichi Takeda ,  Masahiro Nomura

IPC分类号： H03K3/01

CPC分类号： H03K19/0013 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep. A control signal is transmitted to the substrate bias generating circuit such that the substrate bias is made deep when the substrate leakage current is smaller than the subthreshold leakage current and such that the substrate bias is made shallow when the substrate leakage current is larger than the subthreshold leakage current.

摘要翻译： 控制衬底偏置使得漏电流最小。 一种半导体集成电路装置，包括利用泄漏检测用MOSFET检测泄漏电流的漏电检测电路，根据来自漏电检测电路的输出产生控制信号的控制电路，将衬底偏置变化的衬底偏置产生电路 控制信号的控制电路以及具有与各漏电检测用MOSFET相同特性的MOSFET的受控电路。 泄漏检测电路检测衬底偏置变深时包括的衬底漏电流，以及随着衬底偏压变深而减小的亚阈值漏电流。 控制信号被传送到衬底偏置产生电路，使得当衬底漏电流小于亚阈值漏电流时衬底偏压变深，并且当衬底泄漏电流大于次阈值时衬底偏置变浅 漏电流。

公开(公告)号：US20060066380A1

公开(公告)日：2006-03-30

申请号：US10533304

申请日：2003-10-30

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： There is provided a level shifter in which short circuit current and the increase in delay are reduced when a firth power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit has a configuration characterized by including a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source, the switching circuit being controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit, the pull-up and/or pull-down circuit being controlled by the third logic circuit.

摘要翻译： 提供了一种电平转换器，其中当控制电源时，短路电流和延迟增加减小。 在用于将提供第一电源的第一逻辑电路的信号电平转换为提供第二电源的第二逻辑电路的信号电平的电平移位器中，电路具有的特征在于包括开关 电平移位核心电路的GND电源端子和GND电源之间的电路，所述开关电路由在第一电源的控制下产生控制信号的第三逻辑电路控制，以及上拉/下拉电路， 在电平移位核心电路的输出处的下拉电路，上拉和/或下拉电路由第三逻辑电路控制。

公开(公告)号：US06342310B2

公开(公告)日：2002-01-29

申请号：US09770290

申请日：2001-01-29

申请人： Ikurou Hashimoto ,  Kenji Saitou ,  Hiroyuki Takeda ,  Koichi Makii ,  Shunichi Hashimoto ,  Takayuki Yamamoto ,  Masahiro Nomura ,  Kouki Ikeda ,  Masafumi Shimizu

发明人： Ikurou Hashimoto ,  Kenji Saitou ,  Hiroyuki Takeda ,  Koichi Makii ,  Shunichi Hashimoto ,  Takayuki Yamamoto ,  Masahiro Nomura ,  Kouki Ikeda ,  Masafumi Shimizu

IPC分类号： B32B1518

CPC分类号： C23C2/02 ,  C23C2/06 ,  Y10S428/939 ,  Y10T428/12799

摘要： A hot-dip galvanized steel sheet composed of a basis steel sheet containing Si in an amount of 0.05-2.5 mass % and Mn in an amount of 0.2-3 mass % and a hot-dip galvanized zinc layer formed on the surface thereof, wherein said hot-dip galvanized zinc layer is formed in such a way that there is an Si—Mn enriched phase which is found, by observation under a scanning electron microscope or a transmission electron microscope, in the vicinity of the interface in a region no shorter than 50 &mgr;m in the cross section perpendicular to the interface between the basis steel sheet and the hot-dip galvanized zinc layer, said Si—Mn enriched phase containing more than twice as much Si and/or Mn as the basis steel sheet and extending over a length no more than 80% of the length of the interface observed. This hot-dip galvanized steel sheet is free of bare spots even in the case where the basis steel sheet contains Si and Mn in a comparatively large amount and hence is liable to suffering bare spots.

摘要翻译： 一种由含有0.05-2.5质量％的Si和0.2-3质量％的Mn的基础钢板和在其表面上形成的热镀锌锌层构成的热浸镀锌钢板，其中 所述热浸镀锌锌层形成为具有Si-Mn富集相，其通过在扫描型电子显微镜或透射型电子显微镜下观察而在不短的区域的界面附近发现 在与基底钢板和热镀锌锌层之间的界面垂直的截面中，超过50um的所述Si-Mn富集相含有基本钢板的Si和/或Mn的两倍以上并且延伸 长度不超过界面观察长度的80％。 即使在基础钢板中含有较多量的Si和Mn的情况下，该热浸镀锌钢板也无斑点，因此容易产生裸露斑点。

公开(公告)号：US5410715A

公开(公告)日：1995-04-25

申请号：US8387

申请日：1993-01-25

申请人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

发明人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.

摘要翻译： 中断控制器包括一个电路，用于保存通过指定从多个中断请求中的每一个的多个优先级中选择的一个优先级获得的信息，以及用于指示是否允许具有至少一个预定的中断请求的中断请求的嵌套的标志 优先考虑多项优先事项。 基于保持在电路中的优先级信息和保持在标志中的信息，控制器操作，使得当在执行具有预定优先级的中断处理的过程中产生中断请求时，如果该标志位于第一 条件是，只有当所产生的中断请求的优先级高于预定优先级时，控制器才确认产生的中断请求，并且如果标志处于第二状态，则控制器不仅在生成的中断请求的优先级 中断请求高于预定优先级，而且当所产生的中断请求的优先级与预定优先级相同时。

公开(公告)号：US5159688A

公开(公告)日：1992-10-27

申请号：US691284

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

公开(公告)号：US5107453A

公开(公告)日：1992-04-21

申请号：US379114

申请日：1989-07-13

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F9/302

CPC分类号： G06F7/535 ,  G06F9/3001 ,  G06F2207/5353

摘要： A data processor using a temporary register for temporarily storing a dividend data and a divisor data, sign flags for indicating respective signs of the dividend and the divisor, and an arithmetic and logic unit (ALU) coupled to the temporary register and having an arithmetic logic operation function required for execution of a division operation and a two's compliment obtaining operation. A microsequencer is provided to control the ALU so as to cause the ALU to execute a given instruction. The microsequencer generates a two's complement obtaining operation instruction signal, and an operation control circuit is coupled to the sign flags and is connected to receive the two's complement obtaining operation instruction signal. The operation control circuit operates to control the ALU in accordance with an output of the sign flags so as to cause the ALU to execute a two's complement obtaining operation, or to substantially invalidate the two's complement obtaining operation of the ALU regardless of the two's complement obtaining operation instruction signal.

公开(公告)号：US4131466A

公开(公告)日：1978-12-26

申请号：US638362

申请日：1975-12-08

申请人： Masahiro Nomura ,  Yutaka Hirabayashi

发明人： Masahiro Nomura ,  Yutaka Hirabayashi

IPC分类号： G03F7/016 ,  G03C5/34 ,  G03C5/24 ,  G03F1/00

CPC分类号： G03F7/016 ,  G03C2001/0471

摘要： A lithographic photographic material has a photosensitive layer comprising gelatin having an isoelectric point of at least 7 and a condensation product formed between a diazonium salt of a para-aminodipheynylamine derivative and an aldehyde. The photosensitive layer can be photoinsolubilized and will form a photo-relief.A method for using the lithographic photographic material comprises partially photoinsolubilizing the photosensitive layer and then immersing it in a bath of an acid or direct dye to form level dying, washing the dye material with water to remove unexposed areas, thereby forming an image composed of the dye photoinsolubilized resin layer corresponding to the exposed areas.

摘要翻译： 平版照相材料具有包含等电点至少为7的明胶的感光层和在对氨基二乙炔基胺衍生物的重氮盐与醛之间形成的缩合产物。 感光层可以光固化并形成光浮雕。

公开(公告)号：US4120041A

公开(公告)日：1978-10-10

申请号：US747059

申请日：1976-12-03

申请人： Masao Hayakawa ,  Masahiro Nomura

发明人： Masao Hayakawa ,  Masahiro Nomura

IPC分类号： H05K1/14 ,  H05K1/18 ,  G06F15/00 ,  H05K1/04

CPC分类号： H05K1/145 ,  H05K1/18 ,  H05K2201/10037 ,  H05K2201/10053 ,  H05K2201/10136 ,  H05K2201/10689

摘要： In a semiconductor device of the Dual In-line Plug-in Package type, input terminals for receiving, for example, key input signals derived from key input means are aligned on a side of the semiconductor device, and output terminals for developing, for example, driving signals for display means are aligned on another side of said semiconductor device. The input terminals and the output terminals function, in combination, not only to electrically connect the key input means, the semiconductor device and the display means with one another, but also to mechanically connect a circuit board for supporting the key input means and another circuit board for supporting the display means with each other.

摘要翻译： 在双列直插式封装类型的半导体器件中，用于接收例如从键输入装置导出的键输入信号的输入端子在半导体器件的一侧对齐，并且例如用于显影的输出端子 ，用于显示装置的驱动信号在所述半导体器件的另一侧对准。 输入端子和输出端子组合起来不仅将键输入装置，半导体装置和显示装置彼此电连接，而且机械地连接用于支撑键输入装置的电路板和另一电路 用于支持显示装置的板。

公开(公告)号：US09166278B2

公开(公告)日：2015-10-20

申请号：US13824136

申请日：2011-09-07

申请人： Eiichi Furukawa ,  Masahiro Nomura

发明人： Eiichi Furukawa ,  Masahiro Nomura

IPC分类号： H01Q13/00 ,  H01Q1/24 ,  H01P11/00 ,  H04B1/40 ,  H01P3/12

CPC分类号： H01Q1/24 ,  H01P3/12 ,  H01P11/002 ,  H04B1/40

摘要： The purpose of the present invention is to reduce the cost of a product while ensuring reliability of the product as a wireless transmission/reception apparatus. Provided is communication apparatus (ODU) (1) installed outside, which includes a case that houses a transmission unit for transmitting a signal and a reception unit for receiving the signal, and a waveguide connected to an external antenna and configured to receive/transmit a signal. In the apparatus, the waveguide is formed integrally with the case, and taper (16) is formed in a part of the tube hole of the waveguide.

摘要翻译： 本发明的目的是在确保作为无线发送/接收装置的产品的可靠性的同时降低产品的成本。 提供了安装在外部的通信装置（ODU）（1），其包括容纳用于发送信号的发送单元的壳体和用于接收信号的接收单元，以及连接到外部天线并被配置为接收/发送 信号。 在该装置中，波导与壳体一体地形成，并且在波导的管孔的一部分中形成有锥形部（16）。