公开(公告)号：US20240077564A1

公开(公告)日：2024-03-07

申请号：US17901070

申请日：2022-09-01

申请人： Chien-Wei Chen ,  Yao-Kuang Huang ,  Chung-Yuan Lee ,  Yeh-Giin Ngo ,  Yin-Chen Hsu

发明人： Chien-Wei Chen ,  Yao-Kuang Huang ,  Chung-Yuan Lee ,  Yeh-Giin Ngo ,  Yin-Chen Hsu

IPC分类号： G01R33/563 ,  A61B5/055 ,  G01R33/567

CPC分类号： G01R33/5635 ,  A61B5/055 ,  G01R33/56308 ,  G01R33/5673

摘要： A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

公开(公告)号：US08802528B2

公开(公告)日：2014-08-12

申请号：US12725627

申请日：2010-03-17

申请人： Hsin-Huei Chen ,  Chung-Yuan Lee

发明人： Hsin-Huei Chen ,  Chung-Yuan Lee

IPC分类号： H01L21/336 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/2815 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7846

摘要： A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.

摘要翻译： PMOS场效应晶体管包括衬底，第一氮化物层，台面结构，两个栅极氧化物膜，栅极堆叠层和第二氮化物层。 衬底具有氧化物层和第一掺杂区域。 第一氮化物层位于氧化物层上。 台面结构包括第一应变Si-Ge层，外延Si层和第二应变Si-Ge层。 第一应变Si-Ge层位于氧化物层和第一氮化物层上。 外延Si层位于第一应变Si-Ge层上。 第二应变Si-Ge层位于外延Si层上。 在第二应变Si-Ge层的表面层中，存在第二掺杂区域。 两个栅氧化膜位于台面结构的两侧。

公开(公告)号：US08691705B2

公开(公告)日：2014-04-08

申请号：US13118604

申请日：2011-05-31

申请人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： C23F1/26 ,  H01L21/32134

摘要： A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

摘要翻译： 图案化具有铪和钼的金属合金材料层的方法。 该方法包括在基板上的具有铪和钼的金属合金材料层上形成图案化掩模层。 图案化掩模层用作掩模，并且使用具有铪和钼的金属合金材料层上的蚀刻剂进行蚀刻处理，以形成具有铪和钼的金属合金层。 蚀刻剂至少包括硝酸，氢氟酸和硫酸。 去除图案化的掩模层。

公开(公告)号：US08466504B2

公开(公告)日：2013-06-18

申请号：US13231968

申请日：2011-09-14

申请人： Chia-Ming Yang ,  Yao-Hsien Wang ,  Chen-Kang Wei ,  Chien-Chi Lee ,  Ming Yean ,  Yi-Wei Chuang ,  Hsiao-Lung Chiang ,  Hung-Chang Liao ,  Chung-Yuan Lee ,  Ming-Chi Chao

发明人： Chia-Ming Yang ,  Yao-Hsien Wang ,  Chen-Kang Wei ,  Chien-Chi Lee ,  Ming Yean ,  Yi-Wei Chuang ,  Hsiao-Lung Chiang ,  Hung-Chang Liao ,  Chung-Yuan Lee ,  Ming-Chi Chao

IPC分类号： H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10876 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083

摘要： A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.

摘要翻译： 具有掺杂剂停止层的DRAM包括衬底，沟槽型晶体管和电连接到沟槽型晶体管的电容器。 沟槽型晶体管包括嵌入在衬底中的栅极结构。 源极掺杂区域和漏极掺杂区域设置在栅极结构的两侧的衬底中。 硼掺杂区域设置在源极掺杂区域下方。 掺杂剂停止层设置在硼掺杂区域内或硼掺杂区域的下方。 掺杂剂停止层包括选自C，Si，Ge，Sn，Cl，F和Br的掺杂剂。

公开(公告)号：US08343871B2

公开(公告)日：2013-01-01

申请号：US12717923

申请日：2010-03-04

申请人： Tah-Te Shih ,  Chung-Yuan Lee

发明人： Tah-Te Shih ,  Chung-Yuan Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0337

摘要： A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

摘要翻译： 一种制造半导体器件的方法包括在器件层上形成第一掩模图案，在第一掩模图案上形成第二掩模图案，蚀刻未被第一和第二掩模图案覆盖的器件层，从而形成第一沟槽，修整 第一掩模图案以形成中间掩模图案，沉积材料层以填充第一沟槽，抛光材料层以暴露中间掩模图案的顶表面，去除中间掩模图案以形成开口，蚀刻器件层 通过开口形成第二沟槽。

公开(公告)号：US08343829B2

公开(公告)日：2013-01-01

申请号：US13171405

申请日：2011-06-28

申请人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

发明人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

摘要： A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

摘要翻译： 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

公开(公告)号：US20120280297A1

公开(公告)日：2012-11-08

申请号：US13231968

申请日：2011-09-14

申请人： Chia-Ming Yang ,  Yao-Hsien Wang ,  Chen-Kang Wei ,  Chien-Chi Lee ,  Ming Yean ,  Yi-Wei Chuang ,  Hsiao-Lung Chiang ,  Hung-Chang Liao ,  Chung-Yuan Lee ,  Ming-Chi Chao

发明人： Chia-Ming Yang ,  Yao-Hsien Wang ,  Chen-Kang Wei ,  Chien-Chi Lee ,  Ming Yean ,  Yi-Wei Chuang ,  Hsiao-Lung Chiang ,  Hung-Chang Liao ,  Chung-Yuan Lee ,  Ming-Chi Chao

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083

摘要： A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.

摘要翻译： 具有掺杂剂停止层的DRAM包括衬底，沟槽型晶体管和电连接到沟槽型晶体管的电容器。 沟槽型晶体管包括嵌入在衬底中的栅极结构。 源极掺杂区域和漏极掺杂区域设置在栅极结构的两侧的衬底中。 硼掺杂区域设置在源极掺杂区域下方。 掺杂剂停止层设置在硼掺杂区域内或硼掺杂区域的下方。 掺杂剂停止层包括选自C，Si，Ge，Sn，Cl，F和Br的掺杂剂。

公开(公告)号：US20110159691A1

公开(公告)日：2011-06-30

申请号：US12717923

申请日：2010-03-04

申请人： Tah-Te Shih ,  Chung-Yuan Lee

发明人： Tah-Te Shih ,  Chung-Yuan Lee

IPC分类号： H01L21/308 ,  C23F1/00

CPC分类号： H01L21/31144 ,  H01L21/0337

摘要： A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

摘要翻译： 一种制造半导体器件的方法包括在器件层上形成第一掩模图案，在第一掩模图案上形成第二掩模图案，蚀刻未被第一和第二掩模图案覆盖的器件层，从而形成第一沟槽，修整 第一掩模图案以形成中间掩模图案，沉积材料层以填充第一沟槽，抛光材料层以暴露中间掩模图案的顶表面，去除中间掩模图案以形成开口，蚀刻器件层 通过开口形成第二沟槽。

公开(公告)号：US20100025778A1

公开(公告)日：2010-02-04

申请号：US12183074

申请日：2008-07-31

申请人： Chao-Sung Lai ,  Hsing-Kan Peng ,  Shian-Jyh Lin ,  Chung-Yuan Lee

发明人： Chao-Sung Lai ,  Hsing-Kan Peng ,  Shian-Jyh Lin ,  Chung-Yuan Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor includes a gate structure of HfMoN. The work function of the gate structure can be modulated by doping the HfMoN with dopants including nitride, silicon or germanium. The gate structure of HfMoN of the present invention is applicable to PMOS, NMOS or CMOS transistors.

摘要翻译： 晶体管包括HfMoN的栅极结构。 可以通过掺杂包括氮化物，硅或锗的掺杂剂来掺杂HfMoN来调制栅极结构的功函数。 本发明的HfMoN的栅极结构可应用于PMOS，NMOS或CMOS晶体管。

公开(公告)号：US20080315284A1

公开(公告)日：2008-12-25

申请号：US11953886

申请日：2007-12-11

申请人： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

发明人： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

摘要： A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.

摘要翻译： 闪存单元包括衬底，设置在衬底上方的T形控制栅极，嵌入在T形控制栅极的下凹槽中的浮置栅极，在T形控制栅极和浮置栅极之间的介电层; T形控制栅极上方的覆盖层，T形控制栅极和衬底之间的控制栅极氧化物，浮置栅极和衬底之间的浮置栅极氧化物，覆盖覆盖层和浮动栅极的衬底，以及 与浮动栅极相邻的源极/漏极区域。 浮动栅极具有与电介质层的一侧共面的垂直壁表面。