公开(公告)号：US20110226736A1

公开(公告)日：2011-09-22

申请号：US13118604

申请日：2011-05-31

申请人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： C23F1/02 ,  C23F1/26

CPC分类号： C23F1/26 ,  H01L21/32134

摘要： A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

摘要翻译： 图案化具有铪和钼的金属合金材料层的方法。 该方法包括在基板上的具有铪和钼的金属合金材料层上形成图案化掩模层。 图案化掩模层用作掩模，并且使用具有铪和钼的金属合金材料层上的蚀刻剂进行蚀刻处理，以形成具有铪和钼的金属合金层。 蚀刻剂至少包括硝酸，氢氟酸和硫酸。 去除图案化的掩模层。

公开(公告)号：US20090146101A1

公开(公告)日：2009-06-11

申请号：US12103681

申请日：2008-04-15

申请人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： C09K13/08

CPC分类号： C23F1/26 ,  H01L21/32134

摘要： An etchant for etching a metal alloy having hafnium and molybdenum includes 20 to 80 percent by weight of nitric acid, 1 to 49 percent by weight of hydrofluoric acid, 1 to 96 percent by weight of sulfuric acid, and 1 to 30 percent by weight of water, based on the total weight of the etchant.

摘要翻译： 用于蚀刻具有铪和钼的金属合金的蚀刻剂包括20至80重量％的硝酸，1至49重量％的氢氟酸，1至96重量％的硫酸和1至30重量％的 水，基于蚀刻剂的总重量。

公开(公告)号：US08691705B2

公开(公告)日：2014-04-08

申请号：US13118604

申请日：2011-05-31

申请人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： C23F1/26 ,  H01L21/32134

摘要： A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

摘要翻译： 图案化具有铪和钼的金属合金材料层的方法。 该方法包括在基板上的具有铪和钼的金属合金材料层上形成图案化掩模层。 图案化掩模层用作掩模，并且使用具有铪和钼的金属合金材料层上的蚀刻剂进行蚀刻处理，以形成具有铪和钼的金属合金层。 蚀刻剂至少包括硝酸，氢氟酸和硫酸。 去除图案化的掩模层。

公开(公告)号：US07911028B2

公开(公告)日：2011-03-22

申请号：US12183077

申请日：2008-07-31

申请人： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

发明人： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

IPC分类号： H01L29/94

CPC分类号： H01L28/75 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66181 ,  H01L29/785

摘要： A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.

摘要翻译： 一种半导体器件，包括金属化合物Hfx1Moy1Nz1作为电极。 电极的功函数可以通过掺杂含有氮，硅或锗的掺杂剂的金属化合物来调节。 本发明的金属化合物可应用于PMOS，NMOS，CMOS晶体管和电容器。

公开(公告)号：US20100025815A1

公开(公告)日：2010-02-04

申请号：US12183077

申请日：2008-07-31

申请人： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

发明人： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

IPC分类号： H01L29/94 ,  H01L21/02 ,  C01B21/00

CPC分类号： H01L28/75 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66181 ,  H01L29/785

摘要： A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.

摘要翻译： 一种半导体器件，包括金属化合物Hfx1Moy1Nz1作为电极。 电极的功函数可以通过掺杂含有氮，硅或锗的掺杂剂的金属化合物来调节。 本发明的金属化合物可应用于PMOS，NMOS，CMOS晶体管和电容器。

公开(公告)号：US20100025778A1

公开(公告)日：2010-02-04

申请号：US12183074

申请日：2008-07-31

申请人： Chao-Sung Lai ,  Hsing-Kan Peng ,  Shian-Jyh Lin ,  Chung-Yuan Lee

发明人： Chao-Sung Lai ,  Hsing-Kan Peng ,  Shian-Jyh Lin ,  Chung-Yuan Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor includes a gate structure of HfMoN. The work function of the gate structure can be modulated by doping the HfMoN with dopants including nitride, silicon or germanium. The gate structure of HfMoN of the present invention is applicable to PMOS, NMOS or CMOS transistors.

摘要翻译： 晶体管包括HfMoN的栅极结构。 可以通过掺杂包括氮化物，硅或锗的掺杂剂来掺杂HfMoN来调制栅极结构的功函数。 本发明的HfMoN的栅极结构可应用于PMOS，NMOS或CMOS晶体管。

公开(公告)号：US06696344B1

公开(公告)日：2004-02-24

申请号：US10384947

申请日：2003-03-10

申请人： Shian-Jyh Lin ,  Hsin-Jung Ho ,  Chao-Sung Lai ,  Tzu-Ching Tsai

发明人： Shian-Jyh Lin ,  Hsin-Jung Ho ,  Chao-Sung Lai ,  Tzu-Ching Tsai

IPC分类号： H01L218242

CPC分类号： H01L27/1087

摘要： A method for forming a bottle-shaped trench. A semiconductor substrate having a pad stack layer thereon and a trench in a predetermined position is provided. A first dielectric layer is then formed on the lower sidewalls of the trench. Next, a second dielectric layer is formed to cover the upper sidewalls of the trench and the pad stack layer. Then, a protection layer is formed on the sidewalls portions of the second dielectric layer. The first dielectric layer is then removed to expose the lower portion of trench. Wet stripping is then carried out to increase the radius of the lower portion of the trench thereby forming a bottle-shaped trench.

摘要翻译： 一种用于形成瓶形沟槽的方法。 提供其上具有衬垫叠层的半导体衬底和处于预定位置的沟槽。 然后在沟槽的下侧壁上形成第一电介质层。 接下来，形成第二电介质层以覆盖沟槽和衬垫叠层层的上侧壁。 然后，在第二电介质层的侧壁部分上形成保护层。 然后去除第一电介质层以暴露沟槽的下部。 然后进行湿剥离以增加沟槽下部的半径，从而形成瓶形沟槽。

公开(公告)号：US06716757B2

公开(公告)日：2004-04-06

申请号：US10430874

申请日：2003-05-07

申请人： Shian-Jyh Lin ,  Chao-Sung Lai

发明人： Shian-Jyh Lin ,  Chao-Sung Lai

IPC分类号： H01L21762

CPC分类号： H01L29/66181 ,  H01L21/3065

摘要： A method for forming bottle trenches. The method comprises providing a substrate formed with a pad stack layer on the top, and a deep trench with protective layer on the upper portions of sidewalls thereof, implanting ions into the lower portions of sidewalls and bottom of the trench not covered by the protective layer to amorphize the atomic structure of the sidewalls and bottom, oxidizing the amorphous sidewalls and bottom of the trench to form a bottle-shaped oxide layer thereon, and removing the bottle-shaped oxide layer.

摘要翻译： 一种形成瓶沟的方法。 该方法包括在顶部提供形成有衬垫叠层的衬底和在其侧壁的上部上具有保护层的深沟槽，将离子注入未被保护层覆盖的沟槽的侧壁和底部的下部 使侧壁和底部的原子结构非晶化，氧化无定形侧壁和沟槽底部以在其上形成瓶状氧化物层，并且去除瓶状氧化物层。

公开(公告)号：US20060105530A1

公开(公告)日：2006-05-18

申请号：US10986692

申请日：2004-11-12

申请人： Chao-Sung Lai ,  Woei-Cherng Wu ,  Jer-Chyi Wang ,  Kung-Ming Fan ,  Shian-Jyh Lin

发明人： Chao-Sung Lai ,  Woei-Cherng Wu ,  Jer-Chyi Wang ,  Kung-Ming Fan ,  Shian-Jyh Lin

IPC分类号： H01L21/336

CPC分类号： H01L21/2822 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28238 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

摘要： A method for fabricating a semiconductor device with high-k materials. A high-k dielectric layer is formed on a substrate, followed by a fluorine-containing treatment of the high-k dielectric layer, forming an interface containing Si—F bonds.

摘要翻译： 一种制造具有高k材料的半导体器件的方法。 在基板上形成高k电介质层，接着对高k电介质层进行含氟处理，形成含有Si-F键的界面。

公开(公告)号：US09922803B2

公开(公告)日：2018-03-20

申请号：US13653642

申请日：2012-10-17

申请人： Chi-Hsien Huang ,  Chao-Sung Lai ,  Chien Chou ,  Chu-Fa Chan

发明人： Chi-Hsien Huang ,  Chao-Sung Lai ,  Chien Chou ,  Chu-Fa Chan

IPC分类号： H01L21/00 ,  H01J37/32 ,  C23C16/455

CPC分类号： H01J37/32091 ,  C23C16/45565 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32633

摘要： The invention provides a plasma processing device, wherein the upper electrode and the lower electrode are in the vacuum chamber. The chip is placed in the lower electrode. The first plate is placed between the upper electrode and the lower electrode, and the first plate includes a plurality of first voids. The second plate is placed between the first plate and the lower electrode, and the second plate includes a plurality of second voids. The high frequency power is provided by the upper electrode and the lower electrode in the vacuum chamber, and the plasma is generated between the third plate and the upper electrode. The plasma is filtered by the third void, the first void, and the second void.