公开(公告)号：US09899369B2

公开(公告)日：2018-02-20

申请号：US14860788

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

公开(公告)号：US20170221876A1

公开(公告)日：2017-08-03

申请号：US15484143

申请日：2017-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0207 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7819 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

公开(公告)号：US20170110446A1

公开(公告)日：2017-04-20

申请号：US14938850

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L27/0207 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7819 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

公开(公告)号：US20170084603A1

公开(公告)日：2017-03-23

申请号：US14924708

申请日：2015-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region.

公开(公告)号：US20170084602A1

公开(公告)日：2017-03-23

申请号：US14920902

申请日：2015-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/8249 ,  H01L27/027 ,  H01L29/1095 ,  H01L29/78 ,  H01L29/7816

Abstract: An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.

公开(公告)号：US20160351558A1

公开(公告)日：2016-12-01

申请号：US15144836

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract translation: 翅片型ESD保护装置包括至少一个第一鳍片，至少一个第二鳍片和至少一个栅极结构。 第一翅片设置在半导体衬底上，源极触点接触第一鳍片。 第二鳍片设置在半导体衬底上，漏极接触件接触第二鳍片。 第一鳍片和第二鳍片分别在第一方向上延伸，并且第一鳍片与第二鳍片分离。 栅极结构设置在源极触点和漏极触点之间。 第一鳍片与漏极接触部分开，第二鳍片与源极接触部分离开。

公开(公告)号：US09455246B2

公开(公告)日：2016-09-27

申请号：US14687921

申请日：2015-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

公开(公告)号：US20160260700A1

公开(公告)日：2016-09-08

申请号：US14724825

申请日：2015-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Chen Chang

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/78 ,  H01L29/7818 ,  H01L29/7831 ,  H01L29/7835

Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.

Abstract translation: 一种静电放电保护半导体器件，包括：基板，位于基板上的栅极集电体，分别位于栅极集合体两侧的基板上形成的源极区域和漏极区域，形成在漏极区域中的至少第一掺杂区域， 以及形成在所述衬底中的至少第二掺杂区域。 源极区域和漏极区域包括第一导电类型，第一掺杂区域和第二掺杂区域包括第二导电类型，并且第一导电性和第二导电类型彼此互补。 第一掺杂区域和第二掺杂区域彼此电连接。

公开(公告)号：US09343567B2

公开(公告)日：2016-05-17

申请号：US14454739

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/02 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。