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    Intermittent coating apparatus and intermittent coating method
    51.
    发明授权
    Intermittent coating apparatus and intermittent coating method 失效
    间歇涂布装置和间歇涂布方法

    公开(公告)号：US07041336B2

    公开(公告)日：2006-05-09

    申请号：US10617865

    申请日：2003-07-14

    申请人： Noboru Masuda ,  Masaru Watanabe

    发明人： Noboru Masuda ,  Masaru Watanabe

    IPC分类号： B05D1/26

    CPC分类号： B05C11/1047 ,  B05C5/0258 ,  B05C11/10 ,  B05D1/26 ,  B05D5/00 ,  B05D2252/02

    摘要： The intermittent coating apparatus which includes a nozzle 1 which applies a paint 6 to a base material, a feeding side two-way valve 10 which repeats feeding of the paint 6 to the nozzle 1 and stop of the feeding, a return side two-way valve which 11 repeats discharge of the paint 6 to a return side and stop of the discharge, a paint flow path 12, means to feed the paint 6 into the flow path 12, and paint returning means 5 which repeats suction and return of the paint 6 out of and into the nozzle 1, and is characterized in that switching of the feeding side two-way valve 10 is carried out earlier than that of the return side two-way valve 11 within a range not shorter than 5 msec and not longer than 100 msec at least at a coating start time.

    摘要翻译： 间歇式涂布装置，其具有将涂料6涂布在基材上的喷嘴1，重复向喷嘴1供给涂料6并停止供给的供给侧二通阀10，返回侧双向 阀11重复将油漆6排出到返回侧并停止排出，油漆流动路径12，将油漆6进料到流路12中的装置以及重复抽吸和返回涂料的涂料返回装置5 6，其特征在于，在不短于5毫秒的范围内，进给侧开闭阀10的切换比返回侧开闭阀11的切换早 至少在涂层开始时间超过100毫秒。

    Transmission power control method of wireless communication terminal and a base station therefore
    52.
    发明授权
    Transmission power control method of wireless communication terminal and a base station therefore 失效
    因此，无线通信终端和基站的传输功率控制方法

    公开(公告)号：US06963754B2

    公开(公告)日：2005-11-08

    申请号：US10078381

    申请日：2002-02-21

    申请人： Noboru Masuda ,  Kiyoshi Kawamoto ,  Satoshi Masuda

    发明人： Noboru Masuda ,  Kiyoshi Kawamoto ,  Satoshi Masuda

    IPC分类号： H04B7/26 ,  H04B7/005 ,  H04W36/18 ,  H04W52/08 ,  H04W52/40 ,  H04B7/00

    CPC分类号： H04W52/40 ,  H04W36/18 ,  H04W52/08

    摘要： Disclosed is a transmission power control method which enables communications between a base station and a terminal station to be always performed at a high transfer rate by always assuring an uplink communication path between a base station which can transfer a downlink signal most efficiently and a terminal station. Each of terminal stations 111 to 119 selects a base station which can receive a downlink radio wave with the highest power, and transmits a code for identifying the base station on an uplink signal. When the received power of the uplink radio waves transmitted from the terminal station which has transmitted the code identifying the own station is higher than the threshold value, each of base stations 501 to 503 transmits a control signal for decreasing the power to the terminal station. When the terminal station sends a code for identifying another station or the power of the uplink radio waves received from the terminal station is lower than the threshold value, a control signal for increasing the power is sent to the terminal station. When even one power control signal for giving instruction to decrease the transmission power exists, each terminal station decreases its transmission power. When there is not the power control signal, each terminal station increases its transmission power.

    摘要翻译： 公开了一种发送功率控制方法，其通过始终确保可以最有效地传送下行链路信号的基站与终端站之间的上行链路通信路径，使基站和终端站之间的通信始终以高传输速率进行通信 。 终端站111至119中的每一个选择能够接收具有最高功率的下行链路无线电波的基站，并且在上行链路信号上发送用于识别基站的码。 当从发送了本台站的代码的终端发送的上行无线电波的接收功率高于阈值时，基站501〜503中的每一个向终端站发送降低功率的控制信号。 当终端发送用于识别另一站的码或从终端接收到的上行电波的功率低于阈值时，向终端发送增加电力的控制信号。 当存在用于给出降低发送功率的指令的一个功率控制信号时，每个终端站降低其发送功率。 当没有功率控制信号时，每个终端站增加其发射功率。

    Voltage controlled oscillator and PLL circuit using the same
    53.
    发明授权
    Voltage controlled oscillator and PLL circuit using the same 失效
    压控振荡器和PLL电路使用相同

    公开(公告)号：US06768387B1

    公开(公告)日：2004-07-27

    申请号：US09634544

    申请日：2000-08-08

    申请人： Noboru Masuda ,  Hiroki Yamashita

    发明人： Noboru Masuda ,  Hiroki Yamashita

    IPC分类号： H03B100

    CPC分类号： H03L7/087 ,  H03K3/011 ,  H03K3/0315 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0995

    摘要： The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

    摘要翻译： 本发明涉及一种PLL电路和压控振荡器，其中可以提供当电源电压波动小时引起的时钟信号抖动，并且压控振荡器设置有MOS晶体管，其一端为第一 电源（Vss）连接到输入用于控制振荡频率的控制信号的栅电极，连接在MOS晶体管的另一端和第二电源（Vdd）之间的振荡器和连接到 该振荡器并联并且还具有用于微调控制振荡频率的附加控制装置。

    Clocked logic gate circuit
    54.
    发明授权
    Clocked logic gate circuit 有权
    时钟逻辑门电路

    公开(公告)号：US06476644B2

    公开(公告)日：2002-11-05

    申请号：US09725450

    申请日：2000-11-30

    申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

    发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

    IPC分类号： G11C800

    CPC分类号： H03K19/0963 ,  H03K19/1738

    摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

    摘要翻译： 构成时钟逻辑门电路，使得开关单元由逻辑块和参考MOS晶体管构成，参考MOS晶体管的源极连接到逻辑块的一个输出端，参考MOS晶体管的栅极被连接 到逻辑块的另一个输出端，构成逻辑块的MOS晶体管（输入晶体管）并联连接。 通过这种布置，不需要互补的输入，并且驱动MOS晶体管和输入晶体管（或驱动MOS晶体管和参考MOS晶体管）可以串联连接。 结果，获得比构成便利的双轨逻辑简单的电路，并且可以以比CMOS逻辑电路和路径晶体管逻辑电路更高的速度工作。

    Signal transmission circuit on semiconductor integrated circuit chip
    55.
    发明授权
    Signal transmission circuit on semiconductor integrated circuit chip 失效
    半导体集成电路芯片上的信号传输电路

    公开(公告)号：US06426654B2

    公开(公告)日：2002-07-30

    申请号：US09734889

    申请日：2000-12-13

    申请人： Noboru Masuda

    发明人： Noboru Masuda

    IPC分类号： H03K19096

    CPC分类号： G06F13/4077 ,  H03K19/01855 ,  H04L25/0298

    摘要： Disclosed herein is a dynamic type circuit which transmits a signal between relatively long-distant circuit blocks lying within a semiconductor integrated circuit chip. A whole signal path thereof comprises a plurality of sections. A section formed by a first type of signal line, which is precharged to a high level and to which a decision as to whether it is driven to a low level according to a signal inputted from a preceding section or it is left in floating state, is made, and a section formed by a second type of signal line, which is precharged to a low level in reverse and to which a decision as to whether it is driven to a high level according to a signal inputted from a preceding section or it is left in a floating state, is made, exist in alternate shifts. The respective sections are respectively connected to preceding-stage sections through MOS transistors for driving signal lines for the sections. MOS transistors for precharge are respectively connected to the signal lines for the respective sections at plural positions where a signal line is partitioned into substantially uniform intervals.

    摘要翻译： 这里公开了一种动态类型电路，其在位于半导体集成电路芯片内的相对长的电路块之间传输信号。 其整个信号路径包括多个部分。 由第一类型的信号线形成的部分，其被预先充电到高电平，并且根据从前一部分输入的信号或将其置于浮动状态来决定是否被驱动到低电平， 以及由第二类型的信号线形成的部分，其被反相地预充电到低电平，并且根据从前一部分输入的信号或其是否被驱动到高电平的判定 处于浮动状态，被制成，以交替的方式存在。 各个部分分别通过MOS晶体管连接到前级部分，用于驱动部分的信号线。 用于预充电的MOS晶体管分别连接到信号线被划分成大致均匀间隔的多个位置处的各个部分的信号线。

    IC testing apparatus
    56.
    发明授权
    IC testing apparatus 失效
    IC测试仪器

    公开(公告)号：US06257319B1

    公开(公告)日：2001-07-10

    申请号：US09357906

    申请日：1999-07-21

    申请人： Tadashi Kainuma ,  Noboru Masuda ,  Haruki Nakajima ,  Noriyuki Igarashi ,  Yuichi Nansai

    发明人： Tadashi Kainuma ,  Noboru Masuda ,  Haruki Nakajima ,  Noriyuki Igarashi ,  Yuichi Nansai

    IPC分类号： G01R3102

    CPC分类号： G01R31/2868 ,  G01R31/2849 ,  G01R31/2874

    摘要： An IC testing apparatus 1 for performing a test by applying at least a low temperature stress to ICs to be tested comprising a refrigerant cycle 210 wherein at least a compressor 211, condenser 212, expansion valve 214 and evaporator 215 are connected in this order, and a cold air applying line 220 having a blower 223 for supplying heat exchanged cold air by the evaporator 215 to the ICs to be tested.

    摘要翻译： 用于通过对要测试的IC至少应用低温应力进行测试的IC测试装置1包括至少压缩机211，冷凝器212，膨胀阀214和蒸发器215依次连接的制冷剂循环210，以及 具有用于通过蒸发器215将热交换的冷空气供给到要测试的IC的鼓风机223的冷空气施加管线220。

    Information processing apparatus
    58.
    发明授权
    Information processing apparatus 失效
    信息处理装置

    公开(公告)号：US5604840A

    公开(公告)日：1997-02-18

    申请号：US38839

    申请日：1993-03-29

    申请人： Mitsuo Asai ,  Noboru Masuda ,  Moritoshi Yasunaga ,  Masayoshi Yagyu ,  Minoru Yamada ,  Katsunari Shibata

    发明人： Mitsuo Asai ,  Noboru Masuda ,  Moritoshi Yasunaga ,  Masayoshi Yagyu ,  Minoru Yamada ,  Katsunari Shibata

    IPC分类号： G06N3/04 ,  G06N3/063 ,  G06F15/18

    CPC分类号： G06N3/063 ,  G06N3/0454

    摘要： An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

    摘要翻译： 信息处理装置由输入层，隐藏层和输出层构成，并且以神经元模型进行计算。 在信息处理装置中，包括输入层，隐藏层和输出层的正向网络对外部输入数据执行计算，以确定其输出值，并且包括输出层和隐藏层的反向网络执行计算 对于给定输入预期的输出值来确定学习信号值。 信息处理装置传送前向网络和后向网络之间的输出值和学习值，以修改神经元模型的突触权重。