公开(公告)号：US20100188051A1

公开(公告)日：2010-07-29

申请号：US12308283

申请日：2007-06-13

申请人： Kazuo Yamazaki ,  Hidenori Tanaka ,  Yukihiro Terada ,  Tamiji Nagai ,  Toshio Nagai

发明人： Kazuo Yamazaki ,  Hidenori Tanaka ,  Yukihiro Terada ,  Tamiji Nagai ,  Toshio Nagai

IPC分类号： H02J7/00

CPC分类号： H02M3/1584 ,  H02J7/0072 ,  H02M3/1582 ,  H02M2001/0045

摘要： The present invention provides a highly safe charging circuit with which overcharge of a secondary battery will never occur even when a failure occurs in a transistor or the like that controls the charging voltage or charging current or when a protection circuit does not operate normally. In a secondary battery charging circuit 4 that charges a secondary battery E2 with an input power source voltage, the power source voltage is set to a voltage (e.g. 4.0 V) that is lower than the full-charge voltage (e.g. 4.2 V) of the secondary battery. When the voltage of the secondary battery E2 is lower than the power source voltage, a constant current circuit operates to perform constant current charging without voltage step-up, and when the voltage of the secondary battery E2 is higher than the power source voltage and lower than the full-charge voltage, a voltage step-up circuit operates to perform constant current charging with voltage step-up.

摘要翻译： 本发明提供了一种高度安全的充电电路，即使在控制充电电压或充电电流的晶体管等中发生故障或者当保护电路不能正常工作时，也不会发生二次电池的过度充电。 在以输入电源电压对二次电池E2进行充电的二次电池充电电路4中，电源电压被设定为低于电源电压的全充电电压（例如4.2V）的电压（例如4.0V） 二次电池 当二次电池E2的电压低于电源电压时，恒流电路进行无电压升压的恒流充电，并且当二次电池E2的电压高于电源电压并且较低时 电压升压电路比完全充电电压工作，通过升压升压来进行恒流充电。

公开(公告)号：US07419382B2

公开(公告)日：2008-09-02

申请号：US11589332

申请日：2006-10-30

申请人： Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

发明人： Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

IPC分类号： H01R12/00

CPC分类号： H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/186 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/166

摘要： According to one embodiment, a printed circuit board includes a first dielectric layer, a circuit component mounted on the first dielectric layer, and a second dielectric layer. The first dielectric layer is provided with a via hole which opens at a surface thereof and in which a conductive layer is provided, and a conductive pattern connected electrically to the conductive layer of the via hole. The circuit component is provided with a bump at least a part of which is inserted in the via hole and bonded to an inner surface of the via hole. The second dielectric layer is formed provided with another conductive pattern and laminated to the first dielectric layer to cover the circuit component.

摘要翻译： 根据一个实施例，印刷电路板包括第一电介质层，安装在第一电介质层上的电路部件和第二电介质层。 第一介电层设置有在其表面开口并且其中设置有导电层的通孔以及与通孔的导电层电连接的导电图案。 电路部件设置有凸块，其中至少一部分插入通孔中并结合到通孔的内表面。 第二电介质层被形成为设置有另一个导电图案并层压到第一电介质层以覆盖电路部件。

公开(公告)号：US20070278000A1

公开(公告)日：2007-12-06

申请号：US11807425

申请日：2007-05-29

申请人： Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

发明人： Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

IPC分类号： H05K1/16 ,  H05K7/00

CPC分类号： H05K1/186 ,  H05K1/023 ,  H05K1/0231 ,  H05K3/3442 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/10636 ,  Y02P70/611

摘要： According to one embodiment, a component-embedded printed wiring board includes a base including a component mounting surface, a pair of conductive patterns which is disposed on the component mounting surface of the base, and a circuit component which is mounted on the base so as to be in close contact with the component mounting surface between the conductive patterns and electrically connected to the conductive patterns.

摘要翻译： 根据一个实施例，组件嵌入式印刷线路板包括：基座，其包括部件安装表面;一对导电图案，设置在基座的部件安装表面上;电路部件，安装在基座上， 以与导电图案之间的部件安装表面紧密接触并且电连接到导电图案。

公开(公告)号：US20070230146A1

公开(公告)日：2007-10-04

申请号：US11728546

申请日：2007-03-26

申请人： Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

发明人： Daigo Suzuki ,  Jun Karasawa ,  Hidenori Tanaka

IPC分类号： H05K7/00

CPC分类号： H05K1/186 ,  H05K1/0271 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/10636 ,  Y02P70/611

摘要： According to one embodiment, a printed-wiring board with a built-in component includes a first base material including a component mounting surface. A circuit component is mounted on the component mounting surface of the first base material. A stress relaxation material covers the circuit component. A second base material is stacked on the first base material by interposing, between the first base material and the second base material, an insulating layer covering the stress relaxation material.

摘要翻译： 根据一个实施例，具有内置部件的印刷电路板包括包括部件安装表面的第一基材。 电路部件安装在第一基材的部件安装表面上。 应力松弛材料覆盖电路部件。 第二基材通过在第一基材和第二基材之间插入覆盖应力松弛材料的绝缘层而堆叠在第一基材上。

公开(公告)号：US20070221398A1

公开(公告)日：2007-09-27

申请号：US11701816

申请日：2007-02-01

申请人： Jun Karasawa ,  Daigo Suzuki ,  Hidenori Tanaka

发明人： Jun Karasawa ,  Daigo Suzuki ,  Hidenori Tanaka

IPC分类号： H05K1/00 ,  H05K3/30

CPC分类号： H05K1/111 ,  H05K3/284 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49147

摘要： According to one embodiment, there is provided a printed-wiring board with a component in which an electronic component is mounted on a pattern-forming surface of a base material. In the printed-wiring board, a guiding path for guiding, to the outside, a void formed in mounting the electronic component is formed on the pattern-forming surface.

摘要翻译： 根据一个实施例，提供了一种印刷电路板，其具有将电子部件安装在基材的图案形成表面上的部件。 在印刷电路板中，在图案形成表面上形成用于将安装电子部件形成的空隙引导到外部的引导路径。

公开(公告)号：US20060131173A1

公开(公告)日：2006-06-22

申请号：US10527401

申请日：2003-09-12

申请人： Toshitaka Kawanami ,  Hiroyuki Sakamoto ,  Hidenori Tanaka ,  Kazuo Morichika ,  Takao Saito

发明人： Toshitaka Kawanami ,  Hiroyuki Sakamoto ,  Hidenori Tanaka ,  Kazuo Morichika ,  Takao Saito

IPC分类号： C09D5/44

CPC分类号： H01B13/16 ,  C09D5/4446 ,  C25D13/16

摘要： In view of the above-discussed state of the art, it is an object of the present invention to provide a method of coating an electric wire by which insulated wires excellent in dielectric breakdown voltage can be obtained by a relatively short period of dipping of articles to be coated in an electrodeposition bath. A method of coating an electric wire comprising cationic electrocoating with a cationic electrodeposition coating composition, wherein the cationic electrodeposition coating composition contains a resin composition having a hydratable functional group reducible directly by an electron and results in forming passive coat.

摘要翻译： 鉴于上述现有技术的问题，本发明的目的是提供一种涂覆电线的方法，通过这种方法可以通过相对较短的制品浸渍时间获得介电击穿电压优良的绝缘电线 将其涂覆在电沉积浴中。 一种用阳离子电沉积涂料组合物涂覆包含阳离子电涂层的电线的方法，其中阳离子电沉积涂料组合物含有具有可直接由电子还原的可水合官能团的树脂组合物，并导致形成钝化涂层。

公开(公告)号：US20050211979A1

公开(公告)日：2005-09-29

申请号：US10940963

申请日：2004-09-15

申请人： Hideki Ogawa ,  Hidenori Tanaka

发明人： Hideki Ogawa ,  Hidenori Tanaka

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/66 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H05K3/22 ,  H05K3/34

CPC分类号： H01L21/4864 ,  H01L21/485 ,  H01L23/498 ,  H01L2924/0002 ,  H05K3/225 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/09063 ,  H05K2203/0126 ,  H05K2203/081 ,  Y02P70/613 ,  H01L2924/00

摘要： Disclosed is an IC package including an interpose substrate and lands for external connection disposed on a face of the interpose substrate in a grid pattern, the interpose substrate having a penetration hole on at least a position between the lands for external connection disposed in a grid pattern. Besides, there are disclosed an inspection method of an IC package mounting body mounting this IC package, a repairing method of an IC package mounting body mounting this IC package, and an inspection pin for an IC package mounting body used for such an inspection.

摘要翻译： 公开了一种IC封装，其包括插入基板和用于外部连接的焊盘，其设置在格栅图案的插入基板的表面上，所述插入基板在至少位于用于外部连接的焊盘之间的位置处具有贯穿孔， 。 此外，公开了安装该IC封装的IC封装安装体的检查方法，安装该IC封装的IC封装安装体的修复方法以及用于这种检查的IC封装安装体的检查销。

公开(公告)号：US06275241B1

公开(公告)日：2001-08-14

申请号：US09150252

申请日：1998-09-10

申请人： Hidenori Tanaka

发明人： Hidenori Tanaka

IPC分类号： G09G539

CPC分类号： G06T15/405 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/12

摘要： This invention is a three-dimensional image drawing apparatus that comprises a frame buffer for storing display data corresponding to a display screen in a display apparatus, and a two-dimensional drawing circuit for performing coordinate operations in order to draw specific two-dimensional images in the frame buffer. The apparatus also uses a Z buffer for storing depth data in order to perform three-dimensional drawing to the frame buffer, and a three-dimensional straight line drawing circuit for making three-dimensional drawings to the frame buffer based on the depth data stored in the Z buffer. The apparatus also uses a memory control circuit for controlling access to the buffers, and a bit number altering circuit for altering the number of bits per pixel in the coordinate operations of the two-dimensional drawing circuit either to a number of bits corresponding to the drawing data in the frame buffer or to a number of bits corresponding to the depth data in the Z buffer. The areas of both the frame buffer and Z buffer here are established in the same physical memory.

摘要翻译： 本发明是一种三维图像绘制装置，其包括用于存储与显示装置中的显示屏相对应的显示数据的帧缓冲器，以及用于执行坐标操作以便画出特定二维图像的二维绘制电路 帧缓冲区。 该装置还使用Z缓冲器来存储深度数据，以便对帧缓冲器执行三维绘制;以及三维直线绘制电路，用于基于存储在帧缓冲器中的深度数据将三维绘图制作到帧缓冲器 Z缓冲区。 该装置还使用存储器控制电路来控制对缓冲器的访问，以及位数改变电路，用于将二维绘制电路的坐标操作中的每像素的位数改变为与图形对应的位数 帧缓冲器中的数据或与Z缓冲器中的深度数据相对应的位数。 这里的帧缓冲区和Z缓冲区的区域都建立在相同的物理内存中。

公开(公告)号：US06263490B1

公开(公告)日：2001-07-17

申请号：US09103932

申请日：1998-06-25

申请人： Hidenori Tanaka

发明人： Hidenori Tanaka

IPC分类号： G06F945

CPC分类号： G06F11/0751 ,  G06F11/0721 ,  G06F11/3648 ,  G06F11/366 ,  G09G5/363

摘要： A graphic LSI is for use in an image processing apparatus having a buffer memory circuit for buffering a drawing data in a specific address to display the drawing data as a graphic drawing on a display unit. The graphic LSI comprises a graphic drawing circuit for producing the specific address in accordance with a drawing command and a debug circuit for putting the image processing apparatus into a debug state when the specific address is coincident with a predetermined address.

摘要翻译： 图形LSI用于具有用于缓冲特定地址中的绘图数据的缓冲存储器电路的图像处理装置，以在显示单元上显示绘图数据作为图形。 图形LSI包括用于根据绘制命令产生特定地址的图形绘制电路和用于当特定地址与预定地址一致时将图像处理设备置于调试状态的调试电路。