公开(公告)号：US20240113030A1

公开(公告)日：2024-04-04

申请号：US18310557

申请日：2023-05-02

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hiroki Noguchi ,  Yih Wang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

CPC分类号： H01L23/5381 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16145

摘要： A package structure may include a substrate, a plurality of dies on the substrate, and a memory bridge die including a first input/output structure connected to a first semiconductor die of the plurality of dies, and a second input/output structure connected to a second semiconductor die of the plurality of dies. The first semiconductor die may be connected to the second semiconductor die through the memory bridge die.

公开(公告)号：US11947713B2

公开(公告)日：2024-04-02

申请号：US17883670

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Cheng-En Lee ,  Shih-Lien Linus Lu

IPC分类号： G06F21/73 ,  H04L9/32

CPC分类号： G06F21/73 ,  H04L9/3278

摘要： Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.

公开(公告)号：US20240105815A1

公开(公告)日：2024-03-28

申请号：US18126690

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chin-Yi HUANG ,  Shih Chan WEI ,  Wei Kai SHIH

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/66674 ,  H01L29/0653 ,  H01L29/404 ,  H01L29/7801

摘要： A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer, a first isolation structure in the semiconductor layer, a first gate structure adjacent a first side of the first isolation structure, a first source/drain region adjacent a second side of the first isolation structure, a second source/drain region adjacent the first gate structure, and a first conductive field plate at least partially embedded in the first isolation structure.

公开(公告)号：US11943933B2

公开(公告)日：2024-03-26

申请号：US18098093

申请日：2023-01-17

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Bo-Feng Young ,  Mauricio Manfrini ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Yu-Ming Lin

IPC分类号： H10B53/30 ,  G11C11/22 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC分类号： H10B53/30 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/7869

摘要： A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.

公开(公告)号：US20240096834A1

公开(公告)日：2024-03-21

申请号：US18126767

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih Hsuan HSU ,  Chan-Chung CHENG ,  Chun-Chen LIU ,  Cheng-Hung CHEN ,  Peng-Ren CHEN ,  Wen-Hao CHENG ,  Jong-l MOU

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/81

摘要： A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.

公开(公告)号：US11925032B2

公开(公告)日：2024-03-05

申请号：US17872091

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chung-Chiang Min

IPC分类号： H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC分类号： H10B61/00 ,  G11C11/161 ,  H10N50/01 ,  H10N50/80

摘要： A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.

公开(公告)号：US20240071890A1

公开(公告)日：2024-02-29

申请号：US17898499

申请日：2022-08-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Hung Lin

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436

摘要： A semiconductor package includes a package substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness, and an interposer module mounted on the upper surface layer of the package substrate in the second surface area. The semiconductor package may also include an interposer including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness. The semiconductor package may also include an printed circuit board substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness.

公开(公告)号：US11914941B2

公开(公告)日：2024-02-27

申请号：US17233699

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Rachid Salik ,  Chin-Chang Hsu ,  Cheng-Chi Wu ,  Chien-Wen Chen ,  Wen-Ju Yang

IPC分类号： G06F30/27 ,  G06F30/30 ,  G06T7/00 ,  G06F30/398 ,  G06N20/00 ,  G06F119/18

CPC分类号： G06F30/398 ,  G06F30/27 ,  G06N20/00 ,  G06T7/0004 ,  G06F2119/18 ,  G06T2207/10061 ,  G06T2207/30148

摘要： Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

公开(公告)号：US20240051818A1

公开(公告)日：2024-02-15

申请号：US17884106

申请日：2022-08-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Hsi-Cheng HSU ,  Chen-Wei CHIANG ,  Jui-Chun WENG ,  Hsin-Yu CHEN ,  Chia Yu LIN

IPC分类号： B81B7/02 ,  B81C1/00

CPC分类号： B81B7/02 ,  B81C1/00269 ,  B81C2203/0109 ,  B81B2201/0264

摘要： In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, a micro-electromechanical systems (MEMS) structure defined in the semiconductor layer, a bond ring over the semiconductor layer, and a cap structure over the MEMS structure and bonded to the bond ring. The MEMS structure has an upper surface and the cap structure has a lower surface facing the upper surface of the MEMS structure. Dimples of eutectic material are on the upper surface of the MEMS structure.

公开(公告)号：US11903193B2

公开(公告)日：2024-02-13

申请号：US17863749

申请日：2022-07-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chi-Chung Jen ,  Yu-Chu Lin ,  Y. C. Kuo ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-Jen Tung

IPC分类号： H01L21/28 ,  H10B41/46 ,  H01L29/423 ,  H10B41/30 ,  H01L29/51

CPC分类号： H10B41/46 ,  H01L29/40114 ,  H01L29/42336 ,  H10B41/30 ,  H01L29/513

摘要： A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.