公开(公告)号：US20070119615A1

公开(公告)日：2007-05-31

申请号：US11604375

申请日：2006-11-27

Applicant: Hiroyuki Kobayashi

Inventor： Hiroyuki Kobayashi

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K2201/09245 ,  H05K2201/09672

Abstract: A printed wiring board including: a first VIA for allowing a second wiring to penetrate the printed wiring board from a front surface to a rear surface of the board; a second VIA for allowing the second wiring to penetrate the board from the rear surface to the front surface; an alignment interval where the first and second wirings are arranged on the front and rear surfaces of the board, respectively, and the first and second wiring are substantially parallel to each other in plan view; a first interval provided between the first VIA and the alignment interval; and a second interval provided between the alignment interval and the second VIA, in each of first and second intervals, the first wiring is formed crookedly such that the first wiring and the second wiring have substantially the same length.

Abstract translation: 一种印刷线路板，包括：第一VIA，用于允许第二布线从所述板的前表面延伸到所述印刷电路板的后表面; 第二VIA，用于允许所述第二布线从所述后表面到所述前表面穿透所述板; 第一和第二布线分别布置在板的前表面和后表面上的对准间隔，并且第一和第二布线在平面图中基本上彼此平行; 设置在所述第一VIA和所述对准间隔之间的第一间隔; 以及设置在对准间隔和第二VIA之间的第二间隔，在第一和第二间隔的每一个中，第一布线被弯曲地形成，使得第一布线和第二布线具有基本相同的长度。

公开(公告)号：US07204722B2

公开(公告)日：2007-04-17

申请号：US11088044

申请日：2005-03-23

Applicant: Amid Hashim ,  Robert Ray Goodrich

Inventor： Amid Hashim ,  Robert Ray Goodrich

IPC: H01R24/00 ,  H01R13/625

CPC classification number: H05K1/0228 ,  H01R4/242 ,  H01R13/6467 ,  H01R13/6658 ,  H01R24/64 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communications jack assembly includes: a jack frame having a plug aperture; a dielectric mounting substrate attached to the jack frame; and a plurality of conductors engaged with the mounting substrate, each of the conductors including a fixed end portion mounted with the mounting substrate and a free end portion extending into the plug aperture for electrical contact with a mating plug, each of the free end portions having substantially the same profile and being substantially transversely aligned in side-by-side relationship. A first pair of conductors is sandwiched inside a second pair of conductors. The second pair of conductors includes a crossover, the positioning of crossover being selected to provide differential to common mode crosstalk compensation.

Abstract translation: 通信插座组件包括：具有插头孔的插座框架; 安装在所述插座框架上的电介质安装基板; 以及与安装基板接合的多个导体，每个导体包括安装有安装基板的固定端部和延伸到插头孔中的自由端部，用于与匹配插头电接触，每个自由端部具有 基本上相同的轮廓并且以并排关系基本上横向对齐。 第一对导体被夹在第二对导体内。 第二对导体包括交叉，选择交叉的定位以提供对共模串扰补偿的差分。

公开(公告)号：US20060108694A1

公开(公告)日：2006-05-25

申请号：US11281477

申请日：2005-11-18

Applicant: Chih-Chien Hung ,  Ming-Che Wu

Inventor： Chih-Chien Hung ,  Ming-Che Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L27/10

CPC classification number: H05K1/0228 ,  H01L23/49838 ,  H01L23/5225 ,  H01L23/528 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A symmetrical circuit layout structure includes a number of signal wires, a ground wire and a dielectric layer. The signal wires include a first portion placed on a first plane and a second portion placed on a second plane. The ground wire includes a first portion placed above the first portion of the signal wires and adjacent to the second portion of the signal wires, and a second portion placed below the second portion of the signal wires and adjacent to the first portion of the signal wires. The dielectric layer is placed between the first plane and the second plane.

公开(公告)号：US20050269603A1

公开(公告)日：2005-12-08

申请号：US11131295

申请日：2005-05-18

Applicant: Nam-Soo Kang

Inventor： Nam-Soo Kang

IPC: H01L31/062 ,  H01L31/113 ,  H05K1/11

CPC classification number: H05K1/118 ,  H05K2201/09245

Abstract: A flexible printed circuit film has a first wiring and a second wiring. The first wiring is formed on a layer other than where the second wiring is formed, and crosses the second wiring almost at right angle 90°. This structure of the flexible printed circuit film enables to make electronic devices lighter, smaller, and denser than the conventional one. This structure of the flexible printed circuit film also reduces the interferences among the signals coming from the flexible printed circuit film.

Abstract translation: 柔性印刷电路膜具有第一布线和第二布线。 第一布线形成在除了形成第二布线之外的层上，并且几乎以直角90°与第二布线交叉。 柔性印刷电路膜的这种结构使得能够使电子器件比常规电子器件更轻，更小和更致密。 柔性印刷电路膜的这种结构还减少了来自柔性印刷电路膜的信号之间的干扰。

公开(公告)号：US20040124946A1

公开(公告)日：2004-07-01

申请号：US10329751

申请日：2002-12-27

Inventor： Ryszard Vogel

IPC: H01P005/18

CPC classification number: H05K1/0228 ,  H01P5/187 ,  H05K1/0237 ,  H05K1/162 ,  H05K2201/09245

Abstract: The invention relates to a high frequency component of layered structure, and a method for manufacturing the component. The component comprises at least one dielectric layer parallel to the layers of the layered structure, at least two transmission lines for transmitting electrical signals, at least one capacitor, each of which is formed by overlapping parts of two transmission lines, the overlapping parts being for forming capacitive interaction between the parts, and the overlapping parts being arranged to overlap each other in a transversal direction to a dielectric layer parallel to the layers of the layered structure, the dielectric layer being in between the overlapping parts.

Abstract translation: 本发明涉及分层结构的高频分量及其制造方法。 该组件包括平行于分层结构的层的至少一个电介质层，用于传输电信号的至少两个传输线，至少一个电容器，每个电容器由两条传输线的重叠部分形成，重叠部分用于 在所述部分之间形成电容性相互作用，并且所述重叠部分被布置为在与所述层状结构的层平行的电介质层的横向方向上彼此重叠，所述电介质层位于所述重叠部分之间。

公开(公告)号：US06667443B2

公开(公告)日：2003-12-23

申请号：US10007703

申请日：2001-12-10

Applicant: Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

Inventor： Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

IPC: H05K100

CPC classification number: H05K3/4638 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2201/096 ,  H05K2201/09854 ,  H05K2203/063 ,  H05K2203/065 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T156/1064

Abstract: Single-sided conductor patterned films are prepared, each of which has a conductor pattern formed only one side of a resin film and via hole filled with conductive paste. A single-sided conductor patterned film which has a conductor pattern formed only one side of a resin film and an opening formed in the resin film so as to expose an electrode is laminated on the single-sided conductor patterned films. Moreover, a cover layer with an opening to expose an electrode is laminated on a bottom surface of the single-sided conductor patterned films to form a laminate. Then, by pressing while heating the laminate, a multilayer substrate having the electrodes at both sides thereof can be produced.

公开(公告)号：US20030209796A1

公开(公告)日：2003-11-13

申请号：US10458630

申请日：2003-06-11

Inventor： Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

IPC: H01L023/48 ,  H01L021/311 ,  H01L029/40

CPC classification number: H05K3/4638 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2201/096 ,  H05K2201/09854 ,  H05K2203/063 ,  H05K2203/065 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T156/1064

Abstract: Single-sided conductor patterned films are prepared, each of which has a conductor pattern formed only one side of a resin film and via hole filled with conductive paste. A single-sided conductor patterned film which has a conductor pattern formed only one side of a resin film and an opening formed in the resin film so as to expose an electrode is laminated on the single-sided conductor patterned films. Moreover, a cover layer with an opening to expose an electrode is laminated on a bottom surface of the single-sided conductor patterned films to form a laminate. Then, by pressing while heating the laminate, a multilayer substrate having the electrodes at both sides thereof can be produced.

Abstract translation: 制备单面导体图案化膜，其每一个具有只形成树脂膜的一侧的导体图案和填充有导电浆料的通孔。 在单面导体图案化膜上层叠单面导体图案膜，其具有仅形成树脂膜的一侧的导体图案和形成在树脂膜中以露出电极的开口。 此外，在单面导体图案化膜的底面上层叠具有露出电极的开口的覆盖层，以形成层压体。 然后，通过在加热层叠体的同时按压，可以制造在其两侧具有电极的多层基板。

公开(公告)号：US5673009A

公开(公告)日：1997-09-30

申请号：US509419

申请日：1995-07-31

Applicant: Daniel E. Klas ,  William J. Rose

Inventor： Daniel E. Klas ,  William J. Rose

IPC: H01R13/6469 ,  H01R13/6477 ,  H01R24/00 ,  H05K1/02 ,  H05K1/11 ,  H03H7/00 ,  H04M1/74

CPC classification number: H05K1/0228 ,  H01R13/6469 ,  H01R13/6477 ,  H05K1/117 ,  H05K2201/09245 ,  H05K2201/097 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A connector for communications systems has four input terminals and four output terminals, each arranged in an ordered array. A circuit electrically couples each input terminal to the respective output terminal and cancels crosstalk induced across the adjacent connector terminals. The circuit includes four conductive paths between the respective pairs of terminals. The first and third paths are in relatively close proximity and are substantially spaced from the second and fourth paths. The second and fourth paths are in relatively close proximity.

Abstract translation: 用于通信系统的连接器具有四个输入端子和四个输出端子，每个输出端子以有序阵列布置。 电路将每个输入端子电耦合到相应的输出端子，并且消除在相邻的连接器端子之间引起的串扰。 该电路包括在各对端子之间的四个导电路径。 第一和第三路径相对靠近并且与第二和第四路径基本间隔开。 第二和第四路径相对靠近。

公开(公告)号：US5618185A

公开(公告)日：1997-04-08

申请号：US404547

申请日：1995-03-15

Applicant: Robert A. Aekins

Inventor： Robert A. Aekins

IPC: H01R31/06 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H01R9/09

CPC classification number: H01R13/6467 ,  H01R31/065 ,  H05K1/0228 ,  H05K1/115 ,  H05K1/162 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A connector for communications systems includes four input terminals and four output terminals in ordered arrays. A circuit electrically couples respective input and output terminals and cancels crosstalk induced across adjacent connector terminals. The circuit includes four conductive paths between the respective input and output terminals. Sections of two adjacent paths are in close proximity and cross each other between the input and output terminal. At least two of the paths have sets of vias connected in series between the input and output terminals. The sets of vias are adjacent.

Abstract translation: 用于通信系统的连接器包括四个输入端子和四个具有有序阵列的输出端子。 电路电耦合相应的输入和输出端子并且消除在相邻的连接器端子之间引起的串扰。 该电路包括在相应的输入和输出端之间的四个导电路径。 两个相邻路径的部分在输入和输出端之间彼此靠近并彼此交叉。 至少两个路径具有在输入和输出端子之间串联连接的通孔组。 过孔组相邻。

公开(公告)号：US5571996A

公开(公告)日：1996-11-05

申请号：US375327

申请日：1995-01-17

Applicant: N. Deepak Swamy ,  Victor K. Pecone ,  Darrell Slupek

Inventor： N. Deepak Swamy ,  Victor K. Pecone ,  Darrell Slupek

IPC: H05K1/02 ,  H05K7/14 ,  H05K1/18 ,  H05K1/14

CPC classification number: H05K1/0248 ,  H05K1/0228 ,  H05K7/1429 ,  H05K2201/044 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/09709 ,  H05K2201/09718

Abstract: A circuit board is provided having a plurality of vias and uniformly spaced connector stubs arranged upon one or both outer surfaces of the control board. Sets of trace conductors are formed within the control board between the vias. The trace conductors are arranged in two planes within the control board, wherein trace conductors within one plane are laterally offset from trace conductors in the other plane. Laterally offset trace conductors allow close spacing of the trace conductor planes while maximizing the spacing between trace conductors and corresponding reference conductors also placed within the control board. Additionally, the trace conductors are serpentine-shaped when viewed from a perspective perpendicular to the planar surface of the control board. The serpentine shape, in conjunction with carefully controlled spacing between planes of trace conductors as well as between the trace conductor planes and reference conductors, provides high impedance trace conductors in a limited space area necessary to meet SCSI specifications.

Abstract translation: 设置有布置在控制板的一个或两个外表面上的多个通孔和均匀间隔的连接器短截线的电路板。 在通孔之间的控制板内形成导线组。 迹线导体布置在控制板内的两个平面中，其中一个平面内的迹线导体在另一个平面中横向偏离迹线导体。 横向偏移迹线导体允许迹线导体平面的紧密间隔，同时最大化迹线导体和也放置在控制板内的相应参考导体之间的间隔。 此外，当从垂直于控制板的平面表面的视角观察时，迹线导体是蛇形的。 蛇纹形状与跟踪导体的平面之间以及轨迹导体平面和参考导体之间的仔细控制的间距结合，在满足SCSI规范所需的有限空间区域内提供高阻抗迹线导体。