公开(公告)号：US20190198081A1

公开(公告)日：2019-06-27

申请号：US16211956

申请日：2018-12-06

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali ,  Frederick A. Ware

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G06F12/08 ,  G06F12/1009 ,  Y02D10/13

Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

公开(公告)号：US10325645B2

公开(公告)日：2019-06-18

申请号：US15805009

申请日：2017-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/22 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C7/10 ,  G06F1/10 ,  G11C11/409

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

公开(公告)号：US20190181866A1

公开(公告)日：2019-06-13

申请号：US16148977

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03K19/0944 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20

Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

公开(公告)号：US20190179740A1

公开(公告)日：2019-06-13

申请号：US16214558

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/02

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US20190171272A1

公开(公告)日：2019-06-06

申请号：US16193247

申请日：2018-11-16

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G06F1/3234 ,  G06F5/06 ,  G06F1/3287 ,  G11C11/4093

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US10305674B2

公开(公告)日：2019-05-28

申请号：US15498031

申请日：2017-04-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C7/04 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US10254331B2

公开(公告)日：2019-04-09

申请号：US14950138

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/317 ,  G01R31/28 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50 ,  G01R31/26 ,  H03L7/00 ,  G11C29/04

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

公开(公告)号：US10241940B2

公开(公告)日：2019-03-26

申请号：US15314316

申请日：2015-05-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/04 ,  G06F13/40 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

公开(公告)号：US10241563B2

公开(公告)日：2019-03-26

申请号：US15214266

申请日：2016-07-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/32 ,  G06F13/16 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3234

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

公开(公告)号：US20190027210A1

公开(公告)日：2019-01-24

申请号：US16139636

申请日：2018-09-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074 ,  G06F1/32 ,  G11C29/02 ,  G11C7/02 ,  G11C11/4072 ,  G11C7/20

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.