公开(公告)号：US20150180540A1

公开(公告)日：2015-06-25

申请号：US14559756

申请日：2014-12-03

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov

IPC: H04B3/54 ,  H04L12/28 ,  H04L12/10

CPC classification number: H04L12/10 ,  G06F1/3209 ,  G06F1/3287 ,  H04B3/542 ,  H04L12/2838 ,  H04L2012/2843 ,  Y02D10/171

Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.

Abstract translation: 一个实施例是集成片上系统（SoC），其包括通信接口，该通信接口被配置为实现包括被单独通电或断电的功能块的通信协议，以便使用最小功耗来接收和检测信号，以及接收器 识别（ID）检测功能，被配置为确定信号是否适用于SoC驻留的设备。 SoC还包括功率管理功能，其被配置为根据接收机ID检测功能的结果来控制SoC驻留的SoC和/或设备中的哪些功能被激励或断电，以及能够激励 接收和检测信号所需的功能块的最小数量，其中当SoC被通电时，电源可以以低功率状态使用并切换到主电源。

公开(公告)号：US20150118823A1

公开(公告)日：2015-04-30

申请号：US14526053

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

公开(公告)号：US20150115370A1

公开(公告)日：2015-04-30

申请号：US14068340

申请日：2013-10-31

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Qing LIU ,  Ruilong Xie ,  Hyun-Jin Cho

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

Abstract translation: 制造半导体器件的方法可以包括在包括第一半导体材料的衬底上形成第一半导体层，在包括第二半导体材料的第一半导体层上形成第二半导体层，以及在第二半导体层上形成掩模区域和蚀刻 通过第一和第二半导体层在衬底上限定多个间隔开的柱。 该方法可以进一步包括在横向围绕柱和掩模区域形成氧化物层，以及去除掩模区域并在横向相邻的每个柱顶上相应的氧化物层部分上形成内部间隔物。 该方法还可以包括通过相应的内部间隔物之间​​的第二半导体层进行蚀刻，以从每个支柱形成第二半导体材料的一对半导体鳍片，以及去除内部间隔物并在每个半导体鳍片之下形成氧化物。

公开(公告)号：US20150108573A1

公开(公告)日：2015-04-23

申请号：US14060874

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

公开(公告)号：US20150108105A1

公开(公告)日：2015-04-23

申请号：US14586231

申请日：2014-12-30

Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD ,  STMICROELECTRONICS, INC.

Inventor： Fuchao WANG ,  Olivier LENEEL ,  Ravi SHANKAR

IPC: H01L23/34 ,  H05B3/02

CPC classification number: H05B3/0014 ,  H01L23/34 ,  H01L23/345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05B1/0227 ,  H05B3/02 ,  H05B3/06 ,  H05B3/12 ,  H05B3/34 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Abstract translation: 提供具有有源电路的集成电路。 加热元件邻近有源电路并且被配置为加热有源电路。 温度传感器也与有源电路相邻并且被配置为测量有源电路的温度。 温度控制器耦合到有源电路并被配置为从温度传感器接收温度信号。 温度控制器操作加热元件以加热有源电路以将有源电路的温度保持在所选择的温度范围内。

公开(公告)号：US20150104966A1

公开(公告)日：2015-04-16

申请号：US14513988

申请日：2014-10-14

Applicant: STMicroelectronics, Inc. ,  Tatung Company

Inventor： Oleg Logvinov ,  Tai-Jee Pan

IPC: H01R13/621 ,  H01R43/26

CPC classification number: H01R43/26 ,  H01R13/621 ,  H01R23/7073 ,  H01R31/06 ,  Y10T29/49174

Abstract: Embodiments of the present disclosure include an apparatus and a method for connecting a first device and second device. An apparatus includes an angled connector configured to connect to a first device to a second device, the first device and the second device configured to communicate through signal paths in the connector, the signal paths configured to pass digital data signals, a fastening device configured to secure the angled connector to the first device.

Abstract translation: 本公开的实施例包括用于连接第一设备和第二设备的设备和方法。 一种装置包括被配置为将第一装置连接到第二装置的成角度连接器，所述第一装置和第二装置被配置成通过连接器中的信号路径进行通信，所述信号路径被配置为传递数字数据信号，紧固装置被配置为 将成角度的连接器固定到第一个设备。

公开(公告)号：US09006816B2

公开(公告)日：2015-04-14

申请号：US13852645

申请日：2013-03-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US20150087205A1

公开(公告)日：2015-03-26

申请号：US14035281

申请日：2013-09-24

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: B24B37/005

CPC classification number: B24B37/005 ,  B24B27/0076 ,  B24B49/04

Abstract: An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control.

Abstract translation: 自适应均匀抛光系统配备有反馈控制，以在抛光操作期间应用局部调整。 所公开的自适应均匀抛光系统特别适用于半导体工业。 这种自适应均匀抛光系统包括保持半导体晶片的可旋转头部和被构造成与晶片的暴露表面接触的处理单元。 处理单元包括可旋转的宏观垫和多个可旋转的微垫，其可以以不同的转速和压力抛光暴露表面的不同部分。 因此，通过将定制的处理应用于不同的区域，可以增强暴露表面的均匀性。 定制处理可以包括使用不同的垫材料和几何形状。 自适应均匀抛光系统的参数是可编程的，基于在制造过程中的其他操作的原位数据或数据，使用先进的过程控制。

公开(公告)号：US20150076675A1

公开(公告)日：2015-03-19

申请号：US14027975

申请日：2013-09-16

Applicant: STMicroelectronics, Inc.

Inventor： Rogelio Real ,  William Cabreros

IPC: H01L23/00

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed to leadframe packages with wettable sides and methods of manufacturing same. In one embodiment, the leads of the leadframe packages have recesses with a curved profile formed therein. The recesses are plated with a solder wettable layer of conductive material that enables solder to flow along the surface during surface mounting of the package to a board, such as a PCB.

Abstract translation: 本公开的实施例涉及具有可湿侧的引线框封装及其制造方法。 在一个实施例中，引线框封装的引线具有形成在其中的弯曲轮廓的凹部。 这些凹槽镀有导电材料的焊料可润湿层，其使得焊料能够在将封装表面安装到诸如PCB的板的过程中沿表面流动。

公开(公告)号：US08952420B1

公开(公告)日：2015-02-10

申请号：US13953551

申请日：2013-07-29

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 可以将第一薄外延层切割并用于通过弹性弛豫向finFET的相邻沟道区施加应变。 该结构表现出优选的设计范围，用于增加应变在翅片高度上的诱导应变和均匀性。