公开(公告)号：US5332470A

公开(公告)日：1994-07-26

申请号：US149707

申请日：1993-11-09

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/66 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  Y10S438/975

Abstract: Process for the manufacture of calibration structures particularly for the calibration of machines for measuring alignment in integrated circuits in general, the peculiarity of which consists in the fact that calibration structures are provided in which the alignment of one layer with respect to another layer is set to a known extent by means of a single masking.

Abstract translation: 用于制造校准结构的方法，特别是用于校准用于在集成电路中测量对准的机器，其特征在于提供校准结构，其中一层相对于另一层的对准被设置为 已知的程度通过一个单一的掩蔽。

公开(公告)号：US5330938A

公开(公告)日：1994-07-19

申请号：US77934

申请日：1993-06-18

Applicant: Emilio Camerlenghi

Inventor： Emilio Camerlenghi

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

CPC classification number: H01L27/11517 ,  H01L27/115 ,  H01L29/7885

Abstract: The cell comprises a substrate with diffusions of source and drain separated by a channel area a floating gate superimposed over a first part of said channel area and a control gate formed by a first and a second polysilicon strip, respectively, a cell gate oxide between said floating gate and said first part of the channel area, a transistor gate oxide between said control gate and a second part of the channel area, an interpoly oxide between said floating gate and said control gate and a layer of dielectric filler. By means of a process which provides for self-aligned etchings of layers of polysilicon and of oxides there is obtained a floating gate and a control gate self-aligned with one another and with the diffusions of source and drain, as well as with the first oxide.

Abstract translation: 该单元包括一个衬底，源极和漏极的扩散由通道区域分开，叠加在所述沟道区的第一部分上的浮置栅极和由第一和第二多晶硅条形成的控制栅极分别在所述沟道区 浮置栅极和沟道区的所述第一部分，位于所述控制栅极和沟道区域的第二部分之间的晶体管栅极氧化物，所述浮置栅极和所述控制栅极之间的多晶硅氧化物和介电填料层。 通过提供多晶硅和氧化物层的自对准蚀刻的工艺，获得了彼此自对准的浮置栅极和控制栅极以及源极和漏极的扩散，以及第一 氧化物。

公开(公告)号：US5311466A

公开(公告)日：1994-05-10

申请号：US783690

申请日：1991-10-30

Applicant: Virginia Natale ,  Gianluca Petrosino ,  Flavio Scarra

Inventor： Virginia Natale ,  Gianluca Petrosino ,  Flavio Scarra

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  G11C11/34

CPC classification number: G11C16/28

Abstract: The probability of soft-programming of the reference cells of a FLASH-EPROM memory may be excluded by having a decoupling transistor of a type of conductivity opposite to that of the cells functionally connected between the gate of each reference cell and the respective row line. Moreover the elimination of the electrical stresses to which the reference cells are subjected during the repeated programming cycles of the memory cells, increases the stability of the respective reference values of threshold and current level provided by the reference cells, thus increasing the reliability of the device.

Abstract translation: FLASH-EPROM存储器的参考单元的软编程的可能性可以通过具有与功能上连接在每个参考单元的栅极与相应行线之间的单元的导电类型相反的导电类型的去耦晶体管来排除。 此外，消除参考单元在存储器单元的重复编程周期期间受到的电应力增加了由参考单元提供的阈值和电流电平的相应参考值的稳定性，从而增加了器件的可靠性 。

公开(公告)号：US5311073A

公开(公告)日：1994-05-10

申请号：US841621

申请日：1992-02-25

Applicant: Carlo Dallavalle

Inventor： Carlo Dallavalle

IPC: H01L27/088 ,  H01L21/8234 ,  H03K19/003 ,  H03K19/096 ,  H03K17/10

CPC classification number: H03K19/0963 ,  H03K19/0033

Abstract: In a CMOS logic circuit destined to function at a relatively high supply voltage such as to require the formation of graded diffusions in the structure of N-MOS transistors, a NAND configuration is used which comprises a staked pair of N-MOS transistors. This permits to restrict the number of graded diffusions to be formed in N-MOS structures only to the drain regions which are directly connected to an output node. In clocked CMOS circuitry where transfer transistors are normally used between gates, the advantages in terms of enhanced speed and ability of the circuit to be compacted by cutting the number of N-MOS structures necessarily provided with drain extension regions as in prior art circuits, are remarkable.

Abstract translation: 在要以较高电源电压工作的CMOS逻辑电路中，例如要求在N-MOS晶体管的结构中形成渐变扩散，使用NAND配置，其包括一堆堆叠的N-MOS晶体管。 这允许将仅在N-MOS结构中形成的分级扩散的数量限制到直接连接到输出节点的漏极区域。 在通常在栅极之间使用传输晶体管的时钟CMOS电路中，如现有技术电路那样，通过切割必须提供有漏极扩展区域的N-MOS结构的数量，可以提高电路的速度和能力的优点， 卓越。

公开(公告)号：US5266885A

公开(公告)日：1993-11-30

申请号：US851980

申请日：1992-03-12

Applicant: Massimiliano Brambilla ,  Vanni Poletto

Inventor： Massimiliano Brambilla ,  Vanni Poletto

IPC: G05F3/26 ,  G01R1/28 ,  G05F3/30

CPC classification number: G01R1/28 ,  Y10S323/907

Abstract: The generator of reference voltage comprises a first current generator suitable for generating a current that varies linearly with the supply voltage, a first voltage generator suitable for generating a constant voltage with zero thermal drift, a second current generator suitable for generating a current dependent on the voltage with zero thermal drift, a second voltage generator suitable for generating a voltage with given thermal drift, a third current generator suitable for generating a current dependent on the voltage with given thermal drift and means for combining the three currents together so as to produce across an output resistance an output voltage having a value equal to the product of the output resistance by the first and third current, divided by the second current.

公开(公告)号：US5263186A

公开(公告)日：1993-11-16

申请号：US641147

申请日：1991-01-15

Applicant: Silvano Gornati ,  Giorgio Betti ,  Fabrizio Sacchi ,  Gianfranco Vai ,  Maurizio Zuffada

Inventor： Silvano Gornati ,  Giorgio Betti ,  Fabrizio Sacchi ,  Gianfranco Vai ,  Maurizio Zuffada

IPC: H04B1/18 ,  H03G3/30 ,  H04B1/26 ,  H04N5/52 ,  H04B1/16

CPC classification number: H03G3/3068

Abstract: In a dynamic automatic loop for control of the overall gain of an input circuit of a superheterodyne receiver, the response time of the HF-AGC circuit of the TUNER, in response to the action of the TUNER DELAY circuit activated by the IF-AGC in the case of autonomously uncontrollable abrupt increases in the level of the antenna signal from the same HF-AGC of the TUNER, is markedly reduced using an additional TUNER DELAY PLUS circuit able to absorb for a determined interval of time, a discharge current from the storage capacitor the control voltage of the HF-AGC in addition to the discharge current absorbed by the existing TUNER DELAY circuit. The relevant intensity of this additional discharge current and its duration are optimized by way of suitable circuital arrangements in the design of said TUNER DELAY PLUS circuit. The response time is reduced without modifying the time constant of the HF-AGC, which cannot be freely reduced because of inter- and cross-modulation problems.

公开(公告)号：US5258723A

公开(公告)日：1993-11-02

申请号：US919991

申请日：1992-07-27

Applicant: Michelangelo Mazzucco ,  Vanni Poletto ,  Marco Morelli

Inventor： Michelangelo Mazzucco ,  Vanni Poletto ,  Marco Morelli

IPC: G01N27/409 ,  H03F1/08 ,  H03F3/34 ,  H03F3/347 ,  H03F3/45

CPC classification number: H03F1/083 ,  H03F3/45479 ,  H03F2200/261

Abstract: An amplifier including first and second input transistors which are connected to respective first and second feedback amplification circuits associated with respective frequency-compensating capacitances. The second feedback amplification circuit has a two-stage structure and includes an internal compensating capacitance. The three frequency-compensating capacitances can have low values and can thus conveniently be integrated in the same chip as the amplifier. The amplifier can be used, in particular, as an interface between a zirconium-dioxide oxygen sensor and an electronic control unit which have different earth conductors.

公开(公告)号：US5229918A

公开(公告)日：1993-07-20

申请号：US830402

申请日：1992-01-30

Applicant: Pietro Della Bosca ,  Angelo Massironi

Inventor： Pietro Della Bosca ,  Angelo Massironi

IPC: H01L23/34 ,  H01L23/28 ,  H01L23/29 ,  H01L23/433 ,  H01L23/495

CPC classification number: H01L24/49 ,  H01L23/4334 ,  H01L23/49568 ,  H01L2224/05553 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181

Abstract: A metal heat sink baseplate of a resin-encapsulated semiconductor power device, onto which the semiconductor die is bonded, is provided with one or more raised portions near the perimeter of the bound area of the semiconductor die, onto which ground wires may be welded in order to increase the reliability of wire connections realized between ground connecting pads and the metallic heat sink baseplate itself. The raised portions are preferably obtained by deep drawing the metal of the baseplate. A Single-In-Line semiconductor device is shown wherein the deep drawing of the metal heat sink baseplate for realizing a ridge on the assembly face, to be used for realizing wire ground connections is formed in a separation zone between a portion of the metallic baseplate which extends beyond the perimeter of the encapsulating resin body and onto which the fastening means of an external heat sink are arranged, and the remaining part of the baseplate onto which the semiconductor die is bonded. The deep drawing performed in this zone is also instrumental in providing a mechanical decoupling between the two portions of the metallic baseplate for reducing transmission of flection stresses.

Abstract translation: 将半导体管芯接合在其上的树脂封装的半导体功率器件的金属散热器底板在半导体管芯的结合区域的周边附近设置有一个或多个凸起部分，接地线可以焊接到该半导体管芯 以提高接地连接焊盘和金属散热器基板本身之间实现的电线连接的可靠性。 隆起部分优选通过深深拉深基板的金属而获得。 示出了一个单列直列式半导体器件，其中用于实现用于实现线接地连接的组装面上的脊的金属散热器基座的深冲形成在金属基板的一部分之间的分离区 其延伸超过封装树脂体的周边，并且外部散热器的紧固装置被布置在该周边上，并且其上结合有半导体管芯的基板的剩余部分。 在该区域进行的深冲还有助于在金属底板的两个部分之间提供机械去耦，以减少弯曲应力的传递。

公开(公告)号：US5226013A

公开(公告)日：1993-07-06

申请号：US771860

申请日：1991-10-08

Applicant: Maurizio Secol ,  Maurizio Gaibotti

Inventor： Maurizio Secol ,  Maurizio Gaibotti

IPC: G11C16/24

CPC classification number: G11C16/24

Abstract: The bias and precharging circuit comprises a bias part and a precharging part of the bit line together with a sensing amplifier operating by comparison of the voltage of the bit line and a dummy bit line. The precharging part includes components which turn off the bias and precharging parts as soon as the sensing amplifier has read the cell subjected to precharging. The bias part includes components for amplifying the voltage unbalance produced by bias between the bit line and the dummy bit line. It provides a current-mirror to cause said voltage unbalance independently of the precharging part.

Abstract translation: 偏置和预充电电路包括位线的偏置部分和预充电部分以及通过比较位线和虚拟位线的电压来操作的感测放大器。 一旦感测放大器读取了经过预充电的电池，预充电部分就包括关闭偏压和预充电部件的部件。 偏置部分包括用于放大由位线和虚拟位线之间的偏置产生的电压不平衡的部件。 它提供电流镜，以独立于预充电部分而引起所述电压不平衡。

公开(公告)号：US5212455A

公开(公告)日：1993-05-18

申请号：US811153

申请日：1991-12-19

Applicant: Sergio Pernici ,  Germano Nicollini

Inventor： Sergio Pernici ,  Germano Nicollini

IPC: H03F1/08 ,  H03F3/30 ,  H03F3/45

CPC classification number: H03F3/3023 ,  H03F1/086 ,  H03F3/45192 ,  H03F3/45654 ,  H03F2203/45296 ,  H03F2203/45421 ,  H03F2203/45651 ,  H03F2203/45711 ,  H03F2203/45722

Abstract: A power CMOS operational amplifier with a differential output, having an intrinsically stable current absorption under rest conditions, comprises two symmetric branches, each comprising a first folded cascode input inverting stage, a level shifting circuit, a second currant mirror type noninverting amplifying stage and a third output inverting stage, constituted by a complementary pair of transistors, connected in a common source configuration between the supply rails and driven by the output of the second noninverting stage and by the output of the level shifting circuit. Frequency compensation is accomplished by means of two capacitors connected between each of the two output terminals of the amplifier and the output of the first inverting stage and a node of the output branch of the noninverting current mirror stage. A single common mode feedback network stabilizes both symmetric branches of the amplifier.